公开(公告)号：US11770129B2

公开(公告)日：2023-09-26

申请号：US17484581

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Seyed Arash Mirhaj ,  Lei Sun ,  Yuhua Guo ,  Elias Dagher ,  Aram Akhavan ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/06 ,  H03M1/16 ,  H03M1/38 ,  H04B1/40

CPC classification number: H03M1/167 ,  H03M1/38 ,  H04B1/40

Abstract: An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

公开(公告)号：US10651864B2

公开(公告)日：2020-05-12

申请号：US15962967

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Timothy Donald Gathman ,  Yuhua Guo ,  Lai Kan Leung ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03M1/00 ,  H03M1/12 ,  H04B1/16 ,  H03F3/45 ,  H03F3/19 ,  H03F3/24 ,  H03M1/52 ,  G04F5/00 ,  H03M1/54 ,  G11C27/02

Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

公开(公告)号：US10243578B2

公开(公告)日：2019-03-26

申请号：US15440612

申请日：2017-02-23

Applicant: QUALCOMM Incorporated

Inventor： Elias Dagher ,  Yan Wang ,  Mohammad Meysam Zargham ,  Dinesh Jagannath Alladi

IPC: H03M3/00 ,  H03M1/12

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.