公开(公告)号：US11870404B2

公开(公告)日：2024-01-09

申请号：US17320077

申请日：2021-05-13

Applicant: Qualcomm Incorporated

Inventor： Kentaro Yamamoto ,  Aram Akhavan ,  Ganesh Kiran ,  Lei Sun ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03G3/10 ,  H03G3/30 ,  H03F3/19 ,  H03F3/21 ,  H03M1/12

CPC classification number: H03G3/3036 ,  H03F3/19 ,  H03F3/21 ,  H03M1/124 ,  H03F2200/453

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

公开(公告)号：US11569832B1

公开(公告)日：2023-01-31

申请号：US17385799

申请日：2021-07-26

Applicant: Qualcomm Incorporated

Inventor： Aram Akhavan ,  Seyed Arash Mirhaj ,  Lei Sun ,  Elias Dagher

IPC: H03M1/10 ,  H04B1/40

Abstract: An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

公开(公告)号：US20180175867A1

公开(公告)日：2018-06-21

申请号：US15382161

申请日：2016-12-16

Applicant: QUALCOMM Incorporated

Inventor： Emanuele Lopelli ,  Charles Wang ,  Elias Dagher

IPC: H03L7/14 ,  H03L7/099

CPC classification number: H03L7/146 ,  G01S19/44 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/14 ,  H03L2207/50

Abstract: A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a digitally-controlled oscillator (DCO) quantizer to fall between two DCO codes. The method also includes applying the offset to the input frequency of the ADPLL to force the DCO quantizer to have gain.

公开(公告)号：US11962317B2

公开(公告)日：2024-04-16

申请号：US17804779

申请日：2022-05-31

Applicant: QUALCOMM Incorporated

Inventor： Behnam Sedighi ,  Shi Bu ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03M1/08

CPC classification number: H03M1/0854

Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

公开(公告)号：US20220368299A1

公开(公告)日：2022-11-17

申请号：US17320077

申请日：2021-05-13

Applicant: Qualcomm Incorporated

Inventor： Kentaro Yamamoto ,  Aram Akhavan ,  Ganesh Kiran ,  Lei Sun ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03G3/30 ,  H03M1/12 ,  H03F3/19 ,  H03F3/21

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

公开(公告)号：US10312927B1

公开(公告)日：2019-06-04

申请号：US15935988

申请日：2018-03-26

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Elias Dagher ,  Yongjian Tang ,  Dinesh Alladi ,  Masoud Ensafdaran ,  Lei Sun ,  Anand Meruva ,  Yuhua Guo ,  Balasubramanian Sivakumar

IPC: H03K4/08 ,  H03M1/10

Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

公开(公告)号：US20230100825A1

公开(公告)日：2023-03-30

申请号：US17484581

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Seyed Arash Mirhaj ,  Lei Sun ,  Yuhua Guo ,  Elias Dagher ,  Aram Akhavan ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/16 ,  H03M1/38

Abstract: An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

公开(公告)号：US20230024282A1

公开(公告)日：2023-01-26

申请号：US17385799

申请日：2021-07-26

Applicant: Qualcomm Incorporated

Inventor： Aram Akhavan ,  Seyed Arash Mirhaj ,  Lei Sun ,  Elias Dagher

IPC: H03M1/10

Abstract: An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

公开(公告)号：US10277241B1

公开(公告)日：2019-04-30

申请号：US15961631

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Elias Dagher ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/18 ,  H03M1/66 ,  H03M3/00

Abstract: A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

公开(公告)号：US11901909B2

公开(公告)日：2024-02-13

申请号：US17664358

申请日：2022-05-20

Applicant: QUALCOMM Incorporated

Inventor： Igor Gutman ,  Behnam Sedighi ,  Tao Luo ,  Elias Dagher ,  Jeremy Darren Dunworth

IPC: H03M1/18

CPC classification number: H03M1/188 ,  H03M1/185

Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.