公开(公告)号：US08717811B2

公开(公告)日：2014-05-06

申请号：US13785338

申请日：2013-03-05

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.

Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过基于电阻的存储元件的电流。

公开(公告)号：US09378781B1

公开(公告)日：2016-06-28

申请号：US14683008

申请日：2015-04-09

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation; Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C16/28 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C5/10 ,  H03F3/16

CPC classification number: G11C7/08 ,  G11C5/10 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/28 ,  G11C2013/0042 ,  G11C2013/0054 ,  H03F3/45179 ,  H03F3/45775 ,  H03F2203/45212

Abstract: An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve better performance characteristics and read stability without a multistage operation. For example, a sense amplifier may include a second pair of sensing switches cross coupled in parallel with a first pair of sensing switches and a pair of degeneration transistors coupled in line before a pair of load transistors.

Abstract translation: 根据本公开的一些示例的偏移消除读出放大器可以使用双重感测余量结构和正反馈来实现更好的性能特征和读取稳定性而不需要多级操作。 例如，读出放大器可以包括与第一对感测开关并联耦合的第二对感测开关和一对在一对负载晶体管之前串联耦合的退化晶体管。

公开(公告)号：US20140269031A1

公开(公告)日：2014-09-18

申请号：US13835251

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Seung H. Kang ,  Jung Pill Kim

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径检测数据信元的状态和参考信元的状态。 该方法还包括基于数据电压和参考电压确定数据单元的逻辑值。