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公开(公告)号：US11996859B1
公开(公告)日：2024-05-28
申请号：US17119572
申请日：2020-12-11
发明人： Itai Avron , Erez Sabbag
IPC分类号： H03M13/11 , G11C29/36 , G11C29/42 , H03M13/15 , G06F11/10 , G11C13/00 , G11C29/02 , G11C29/44 , G11C29/52
CPC分类号： H03M13/1105 , G11C29/36 , G11C29/42 , H03M13/1515 , H03M13/152 , G06F11/1048 , G11C2013/0057 , G11C29/024 , G11C2029/3602 , G11C29/44 , G11C29/52
摘要： A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.
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公开(公告)号：US20190237137A1
公开(公告)日：2019-08-01
申请号：US16063804
申请日：2016-01-26
发明人： Brent Buchanan , Le Xheng , John Paul Strachan
CPC分类号： G11C13/0026 , G06F17/16 , G06G7/16 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2013/0057 , G11C2213/32 , G11C2213/77
摘要： In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.
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公开(公告)号：US20180277204A1
公开(公告)日：2018-09-27
申请号：US15703070
申请日：2017-09-13
发明人： Marie TAKADA , Masanobu SHIRAKAWA , Hiroshi YAO
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/1006 , G11C13/0026 , G11C13/0033 , G11C13/0069 , G11C2013/0042 , G11C2013/005 , G11C2013/0054 , G11C2013/0057 , G11C2213/71 , G11C2213/78 , G11C2213/79
摘要： A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. The first voltage is different from the second voltage. The first read data has a first value or a second value with the first value being different from the second value. The second read data has the first value or the second value.
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公开(公告)号：US20180277187A1
公开(公告)日：2018-09-27
申请号：US15703438
申请日：2017-09-13
发明人： Kazutaka Ikegami , Hiroki Noguchi , Keiko Abe
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/1655 , G11C11/1675 , G11C11/1693 , G11C13/004 , G11C13/0061 , G11C2013/0057
摘要： According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.
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公开(公告)号：US09972373B2
公开(公告)日：2018-05-15
申请号：US15636970
申请日：2017-06-29
发明人： Thomas Andre , Syed M. Alam , Chitra Subramanian
CPC分类号： G11C11/1675 , G11C7/02 , G11C7/065 , G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C2013/0057 , G11C2207/002
摘要： An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.
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公开(公告)号：US20170330608A1
公开(公告)日：2017-11-16
申请号：US15667600
申请日：2017-08-02
发明人： Chia-Fu LEE , Yu-Der CHIH , Hon-Jarn LIN , Yi-Chun SHIH
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/22 , G11C11/161 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063
摘要： A device includes memory cells, a reference circuit, and a sensing unit. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is turned on when a reference word line is activated. The second reference switch is turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The sensing unit determines a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
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公开(公告)号：US20170249987A1
公开(公告)日：2017-08-31
申请号：US15500074
申请日：2014-11-14
发明人： Yoocharn JEON , James S. IGNOWSKI
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G06F13/1668 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2213/77
摘要： A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.
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公开(公告)号：US09741417B1
公开(公告)日：2017-08-22
申请号：US15293335
申请日：2016-10-14
CPC分类号： G11C11/1673 , G11C7/06 , G11C7/062 , G11C11/16 , G11C11/1655 , G11C11/1693 , G11C13/0026 , G11C13/004 , G11C13/0061 , G11C2013/0042 , G11C2013/0054 , G11C2013/0057
摘要： In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read operation and a second transistor. During the first phase of a memory read operation, the first current path is coupled to one cell and the second current path is coupled to a second cell. The sense amplifier circuit includes a capacitor that during a first phase of a memory read operation, is coupled between two corresponding nodes of the two paths to store a voltage difference between the two nodes. During the second phase, the cell/current path couplings are swapped and the capacitor is coupled to the control terminal of one of the second transistors to control the conductivity of the transistor for adjusting a voltage of an output node to indicate the value of the data being read.
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公开(公告)号：US20170213590A1
公开(公告)日：2017-07-27
申请号：US15324792
申请日：2014-07-31
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0007 , G11C27/02 , G11C2013/0042 , G11C2013/0045 , G11C2013/0057
摘要： According to an example, in a method for determining a resistance state of a cell in a crossbar memory array, a first read voltage may be applied across a cell to sense a first cell current. In addition, a second read voltage may be applied across the cell to sense a second cell current. A difference value between the first cell current and the second cell current may be identified and a resistance state of the cell may be determined based on the difference value.
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公开(公告)号：US09613691B2
公开(公告)日：2017-04-04
申请号：US14671972
申请日：2015-03-27
申请人： Intel Corporation
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
摘要： An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
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