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公开(公告)号：US10433425B1
公开(公告)日：2019-10-01
申请号：US16051876
申请日：2018-08-01
Applicant: QUALCOMM Incorporated
Inventor： Kai Liu , Changhan Hobie Yun , Jonghae Kim , Mario Francisco Velez
Abstract: A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.
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公开(公告)号：US20250080858A1
公开(公告)日：2025-03-06
申请号：US18462199
申请日：2023-09-06
Applicant: QUALCOMM Incorporated
Inventor： Meng-Lin Wu , Venkata Ravi Kiran Dayana , Sandesh Ghimire , Kai Liu , Ching-Fu Chen
IPC: H04N23/741 , H04N23/743
Abstract: This disclosure provides systems, methods, and devices for image signal processing that support high dynamic range (HDR) image processing on image frames with temporally-aligned centers to reduce artifacts resulting from fusing image frames with different temporal centers. In some aspects, a method of image processing includes capturing three or more image frames having at least two different exposure lengths. The three or more image frames are processed to obtain two image frames with temporally-aligned centers, and those two image frames are processed in HDR fusion logic to obtain an output HDR image frame. Other aspects and features are also claimed and described.
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公开(公告)号：US20250078227A1
公开(公告)日：2025-03-06
申请号：US18462218
申请日：2023-09-06
Applicant: QUALCOMM Incorporated
Inventor： Meng-Lin Wu , Venkata Ravi Kiran Dayana , Sandesh Ghimire , Kai Liu , Ching-Fu Chen
Abstract: This disclosure provides systems, methods, and devices for image signal processing that support image signal processing of exposure bracketed image frames. In a first aspect, a method of image processing includes receiving, by at least one processor, image data comprising first image data of a first exposure duration, second image data of a second exposure duration, and third image data of a third exposure duration, wherein the first exposure duration is equal to the third exposure duration; determining, by the at least one processor, fourth image data by subtracting corresponding pixel intensity values of the third image data from the second image data; and determining, by the at least one processor, a first output image frame by combining the fourth image data with the first image data. Other aspects and features are also claimed and described.
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14.发明授权公开(公告)号：US12040268B2
公开(公告)日：2024-07-16
申请号：US17830196
申请日：2022-06-01
Applicant: QUALCOMM Incorporated
Inventor： Je-Hsiung Lan , Jonghae Kim , Kai Liu , Nosun Park
IPC: H01L23/522 , H01C7/00 , H01C17/075 , H01L23/66 , H01L49/02
CPC classification number: H01L23/5228 , H01C7/006 , H01C17/075 , H01L23/5226 , H01L23/66 , H01L28/10 , H01L28/24 , H01L2223/6672
Abstract: An integrated circuit (IC) includes a substrate and a thin film resistor (TFR) device structure. The TFR device structure includes a first portion of a first metallization layer and a second portion of the first metallization layer on the substrate. The TFR device structure also includes a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer. The TFR device structure further includes a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer. The TFR device structure also includes a first portion of a third metallization layer coupling the first portion of the second metallization layer to the second portion of the second metallization layer.
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Patent Agency Ranking
公开(公告)号：US20240038439A1
公开(公告)日：2024-02-01
申请号：US17815784
申请日：2022-07-28
Applicant: QUALCOMM Incorporated
Inventor： Kai Liu , Jui-Yi Chiu , Nosun Park , Je-Hsiung Lan , Jonghae Kim , Periannan Chidambaram
IPC: H01F27/28 , H01L23/498 , H01L49/02 , H01L25/16 , H01F41/064
CPC classification number: H01F27/2866 , H01L23/49861 , H01L23/49838 , H01L28/10 , H01L25/16 , H01F41/064 , H01F27/24
Abstract: Inductor packages employing wire-bonds over a lead frame to form integrated inductor(s), and related integrated circuit (IC) packages and fabrication methods. The inductor package includes one or more integrated inductors each formed from leads of a lead frame coupled together in a pattern through wire bonds to foil a coil(s). An overmold material is formed over the lead frame with the coil(s) formed from the wire-bonded leads to form the inductor package. The overmold material can include a magnetic material to further increase the inductance of the integrated inductor(s). The inductor package can be mounted to a package substrate of an IC package to provide an inductor(s) for a circuit in the IC package. By using a lead frame to form an inductor package, fabrication processes used to form lead frames can also be used to form the inductor package as a less complex, lower cost manufacturing method.
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公开(公告)号：US11177065B2
公开(公告)日：2021-11-16
申请号：US16835227
申请日：2020-03-30
Applicant: QUALCOMM Incorporated
IPC: H01L23/498 , H01F27/22 , H01G4/33 , H01F27/29 , H01G4/252
Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.
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公开(公告)号：US10453774B1
公开(公告)日：2019-10-22
申请号：US16051528
申请日：2018-08-01
Applicant: QUALCOMM Incorporated
IPC: H01L23/373 , H01L23/00 , H01L27/01 , H01L23/66 , H01L23/522
Abstract: Aspects generally relate to an integrated circuit including a glass substrate. On a surface of the glass substrate a thermally conductive insulating layer is formed. At least one metal layer is formed above the thermally conductive insulating layer, and a plurality of thermal bumps extend through the at least one metal layer and couple to the thermally conductive insulating layer to dissipate heat from the substrate.
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公开(公告)号：US12142561B2
公开(公告)日：2024-11-12
申请号：US17705041
申请日：2022-03-25
Applicant: QUALCOMM Incorporated
Inventor： Kai Liu , Je-Hsiung Lan , Jonghae Kim
IPC: H01L23/522 , H01L49/02 , H01L23/00
Abstract: An integrated device that includes a die substrate comprising a plurality of transistors, an interconnection portion coupled to the die substrate, and a packaging portion coupled to the interconnection portion. The interconnection portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.
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19.发明授权公开(公告)号：US10749499B2
公开(公告)日：2020-08-18
申请号：US16115397
申请日：2018-08-28
Applicant: QUALCOMM Incorporated
Abstract: A wideband filter includes a passive substrate and an acoustic resonator chip on the passive substrate. The wideband filter further includes a pair of 3D inductors and a 3D transformer on the passive substrate. The pair of 3D inductors and the 3D transformer are connected to the acoustic resonator chip.
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