公开(公告)号：US11955169B2

公开(公告)日：2024-04-09

申请号：US17210230

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

公开(公告)号：US11049552B1

公开(公告)日：2021-06-29

申请号：US16827959

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4097 ,  G11C7/10 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

公开(公告)号：US10811086B1

公开(公告)日：2020-10-20

申请号：US16523350

申请日：2019-07-26

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Sharad Kumar Gupta ,  Rahul Sahu ,  Pradeep Raj ,  Veerabhadra Rao Boda ,  Adithya Bhaskaran ,  Akshdeepika

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

公开(公告)号：US09916892B1

公开(公告)日：2018-03-13

申请号：US15448526

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Mukund Narasimhan ,  Fahad Ahmed ,  Chulmin Jung

IPC: G11C11/419 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.