公开(公告)号：US10854246B1

公开(公告)日：2020-12-01

申请号：US16421365

申请日：2019-05-23

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C7/06 ,  G11C7/10 ,  H03K19/20

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US11315609B2

公开(公告)日：2022-04-26

申请号：US17039742

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  H03K19/20

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US10832764B2

公开(公告)日：2020-11-10

申请号：US16269463

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14 ,  G05F3/26

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US20220293148A1

公开(公告)日：2022-09-15

申请号：US17774138

申请日：2020-11-09

Applicant: Qualcomm Incorporated

Inventor： Adithya Bhaskaran ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C7/10 ,  G11C7/22

Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

公开(公告)号：US11074967B2

公开(公告)日：2021-07-27

申请号：US17039845

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14 ,  G05F3/26

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US20200372939A1

公开(公告)日：2020-11-26

申请号：US16421365

申请日：2019-05-23

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C7/06 ,  G11C7/10

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US10811086B1

公开(公告)日：2020-10-20

申请号：US16523350

申请日：2019-07-26

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Sharad Kumar Gupta ,  Rahul Sahu ,  Pradeep Raj ,  Veerabhadra Rao Boda ,  Adithya Bhaskaran ,  Akshdeepika

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

公开(公告)号：US11972834B2

公开(公告)日：2024-04-30

申请号：US17774138

申请日：2020-11-09

Applicant: Qualcomm Incorporated

Inventor： Adithya Bhaskaran ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1087 ,  G11C7/1012 ,  G11C7/1084 ,  G11C7/222

Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

公开(公告)号：US20200251163A1

公开(公告)日：2020-08-06

申请号：US16269463

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C11/419 ,  G05F3/26 ,  G11C5/14 ,  G11C7/12

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US10446196B1

公开(公告)日：2019-10-15

申请号：US16164108

申请日：2018-10-18

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Adithya Bhaskaran ,  Sei Seung Yoon

IPC: G11C5/14 ,  G11C11/417

Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.