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公开(公告)号：US20190356412A1
公开(公告)日：2019-11-21
申请号：US16381415
申请日：2019-04-11
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON , Sharon GRAIF , Richard Dominic WIETFELDT
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a data frame to be transmitted over a plurality of data lanes of a multilane serial bus, providing a preamble to precede the data payload in transmission over the multilane serial bus, configuring one or more repurposed bit fields in the data frame to indicate that a multi-bit cyclic redundancy check is provided in the data frame, and transmitting the data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus. At least one bit of the multi-bit cyclic redundancy check is transmitted on two or more data lanes of the plurality of data lanes.
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公开(公告)号：US20190020433A1
公开(公告)日：2019-01-17
申请号：US16025863
申请日：2018-07-02
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON
Abstract: Disclosed are methods and apparatus for calculating sensor timing corrections at a sensor device. The methods and apparatus determine a sampling period as a number of cycles of an internal clock counted while a configured number of samples is captured in a slave device, determine a time interval between samples using an offset from a time of an observed occurrence of a hardware event on a communication link, the offset being received in a command from a master device, and adjust the time interval between samples by iterative digital approximation to correct for differences between timing of the slave device and the master device while concurrently calculating a watermark time corresponding to a sample start time configured by the master device for one or more slave devices.
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公开(公告)号：US20220091952A1
公开(公告)日：2022-03-24
申请号：US17027541
申请日：2020-09-21
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON , Richard Dominic WIETFELDT , Lalan Jee MISHRA
Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.
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公开(公告)号：US20200097434A1
公开(公告)日：2020-03-26
申请号：US16142456
申请日：2018-09-26
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Radu PITIGOI-ARON , Richard Dominic WIETFELDT
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes including a mode that encodes data in a clock signal. A method includes providing a clock signal that controls timing of transactions conducted over a serial bus, transmitting a first pair of data bytes at double data rate over a first wire of the serial bus in a first transaction, modulating the clock signal during the first transaction to provide a modulated clock signal that encodes at least one additional data byte, and transmitting the modulated clock signal over a second wire of the serial bus during the first transaction.
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公开(公告)号：US20190220436A1
公开(公告)日：2019-07-18
申请号：US16201369
申请日：2018-11-27
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON , Lalan Jee MISHRA , Richard Dominic WIETFELDT
IPC: G06F13/42
CPC classification number: G06F13/4291 , G06F13/4282 , G06F2213/0016 , H04L5/0044 , H04L5/0046
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.
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Patent Agency Ranking
公开(公告)号：US20190213165A1
公开(公告)日：2019-07-11
申请号：US16201250
申请日：2018-11-27
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON , Lalan Jee MISHRA , Richard Dominic WIETFELDT
IPC: G06F13/42
CPC classification number: G06F13/4291 , G06F2213/0016
Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A method for arbitrating access to a serial bus includes providing a clock signal on a first line of the serial bus, configuring a line driver coupled to a second line of the serial bus for open-drain operation, transmitting an address header through the line driver in accordance with timing provided by the clock signal, detecting that the second line is driven low in a bit interval corresponding to the at least one most-significant bit, configuring the line driver for push-pull operation after detecting that the second line has been driven low, and increasing rate at which clock pulses are provided in the clock signal after detecting that the second line has been driven low. The address header may include at least one most-significant bit that has a zero-value when a high-priority device is addressed.
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公开(公告)号：US20180181532A1
公开(公告)日：2018-06-28
申请号：US15845866
申请日：2017-12-18
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON
IPC: G06F13/42 , G06F13/364 , G06F13/40
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4072
Abstract: Systems, methods, and apparatus are described that enable communication of flow-control signals over a serial bus that is operated in a phase differential mode of operation. A method performed at a device coupled to the serial bus includes transmitting first data while the serial bus is configured for a phase differential mode of operation, transmitting flow-control signaling after the first data has been transmitted, disabling a driver coupled to a first wire of the serial bus while transmitting the flow-control signaling and while the first wire is in a first signaling state, terminating data transmission when the first wire of the serial bus has transitioned to a second signaling state while the flow-control signaling is transmitted, and transmitting second data over the serial bus after transmitting the flow-control signaling when the first wire of the serial bus has remained in the first signaling state during transmission of the flow-control signaling.
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公开(公告)号：US20190266122A1
公开(公告)日：2019-08-29
申请号：US16204401
申请日：2018-11-29
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON , Richard Dominic WIETFELDT
IPC: G06F13/42
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.
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公开(公告)号：US20190171609A1
公开(公告)日：2019-06-06
申请号：US16162536
申请日：2018-10-17
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Radu PITIGOI-ARON , Richard Dominic WIETFELDT , Sharon GRAIF
IPC: G06F13/42 , G06F13/364 , G06F13/16 , G06F13/40
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus having multiple data lanes includes providing a plurality of frames, each frame being configured to carry up to a maximum number of data bytes, transmitting a first frame over the serial bus, where the first frame is filled with first data bytes, notifying one or more devices of unavailability of an alert opportunity prior to transmitting the first frame, transmitting a second frame over the serial bus, where the first frame includes second data bytes less in number than the maximum number of data bytes, and notifying the one or more devices that the second frame provides an opportunity to launch an alert after transmission of the second data bytes.
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公开(公告)号：US20190129881A1
公开(公告)日：2019-05-02
申请号：US16142419
申请日：2018-09-26
Applicant: QUALCOMM Incorporated
Inventor： Richard Dominic WIETFELDT , Radu PITIGOI-ARON , Lalan Jee MISHRA
Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. An apparatus includes a serial bus, and an originating device and destination device coupled to the serial bus. The originating device may be configured to generate a first virtual GPIO packet that carries a payload representative of signaling state of physical GPIO in the originating device, generate a second virtual GPIO packet that carries a payload representative of an event generated by a processor in the originating device, and transmit the first and second virtual GPIO packets on the serial bus. The destination device may be configured to receive the second virtual GPIO packet from the serial bus, and communicate the event to a processor of the destination device or modify signaling state of physical GPIO in the destination device in accordance with the payload of the second virtual GPIO packet.
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