公开(公告)号：US20190354505A1

公开(公告)日：2019-11-21

申请号：US16381189

申请日：2019-04-11

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Sharon GRAIF ,  Richard Dominic WIETFELDT

IPC: G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.

公开(公告)号：US20190095273A1

公开(公告)日：2019-03-28

申请号：US16123737

申请日：2018-09-06

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Amit GIL ,  David TEB ,  Radu PITIGOI-ARON

IPC: G06F11/10 ,  G06F1/04 ,  G06F11/07 ,  G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. An apparatus has a bus including a first lane and a second lane, a plurality of devices coupled to the bus and, in a first mode of operation, the plurality of devices is configured to exchange data in a signal transmitted on the first lane in accordance with timing provided by a clock signal transmitted on the second lane. The apparatus may include one or more additional lanes connecting two or more devices in the plurality of devices, the two or more devices being configured to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.

公开(公告)号：US20180357199A1

公开(公告)日：2018-12-13

申请号：US15994675

申请日：2018-05-31

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Radu PITIGOI-ARON

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/24

CPC classification number: G06F13/4282 ,  G06F13/24 ,  G06F13/4004 ,  G06F2213/0016

Abstract: Systems, methods, and apparatus for a slave-to-slave communication over a serial communication link are provided. An apparatus includes an interface adapted to couple the apparatus to a serial bus, and a processing circuit. The processing circuit may be configured to receive a request for a slave-to-slave transaction while servicing an in-band interrupt detected on a serial bus, the request for the slave-to-slave transaction indicating a source address and a target address, generate a first frame that includes the source address, the target address and a command code configured to initiate the slave-to-slave transaction between the source slave device and at least one target slave device, and initiate a data transfer on the serial bus between the source slave device and the at least one target slave device by transmitting the first frame on the serial bus.

公开(公告)号：US20190018818A1

公开(公告)日：2019-01-17

申请号：US16008509

申请日：2018-06-14

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Radu PITIGOI-ARON ,  Lior AMARILIO

IPC: G06F13/42 ,  G06F13/26 ,  G06F13/40 ,  G06F13/36

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a non-participating device to cause a master device on an I3C bus transmit a STOP condition that terminates a transaction with a slave device coupled to the I3C bus. A method performed at a master device coupled to a serial bus includes initiating a transaction between the master device and a first slave device, terminating the transaction before completion of the transaction when a second slave device intervenes in the transaction, and servicing the second slave device after terminating the transaction. The transaction may include transmissions of data frames over the serial bus. The second slave device may intervene when it is not a party to the transaction.

公开(公告)号：US20180181533A1

公开(公告)日：2018-06-28

申请号：US15846082

申请日：2017-12-18

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON

IPC: G06F13/42 ,  G06F13/26 ,  G06F13/364 ,  G06F13/40 ,  H04L12/40

CPC classification number: G06F13/4291 ,  G06F13/26 ,  G06F13/364 ,  G06F13/4022 ,  G06F13/4072 ,  H04L12/4013

Abstract: Systems, methods, and apparatus are described that enable communication of flow-control signals over a serial bus. A method performed at a device coupled to the serial bus includes transmitting first data over the serial bus, transmitting one or more preamble bits preceding second data, disabling a driver coupled to a first wire of the serial bus while transmitting the preamble bits and while the first wire is in a first signaling state, terminating data transmission when the first wire has transitioned from the first signaling state to a second signaling state while the preamble bits are being transmitted, and transmitting second data after transmitting the preamble bits when the first wire has remained in the first signaling state during transmission of the preamble bits.

公开(公告)号：US20180173672A1

公开(公告)日：2018-06-21

申请号：US15895856

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Douglas Wayne HOFFMAN

IPC: G06F13/42

CPC classification number: G06F13/4295 ,  G06F13/4291 ,  G06F2213/0016 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

公开(公告)号：US20170364472A1

公开(公告)日：2017-12-21

申请号：US15676741

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Douglas Wayne HOFFMAN

IPC: G06F13/42

CPC classification number: G06F13/4295 ,  G06F13/4291 ,  G06F2213/0016 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

公开(公告)号：US20240089195A1

公开(公告)日：2024-03-14

申请号：US17943565

申请日：2022-09-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT ,  Radu PITIGOI-ARON

IPC: H04L45/24

CPC classification number: H04L45/245 ,  H04L12/40

Abstract: A multi-port data communication apparatus includes a first port having a first physical interface circuit configured to couple the multi-port data communication apparatus to a first serial bus that has a first line and a second line, a second port having a second physical interface circuit configured to couple the multi-port data communication apparatus to a second serial bus that has a first line and a second line, and a controller. The controller is configured to use the first port during a first transaction restricted to transmissions over the first serial bus and use the first port and the second port in a second transaction in which data is transmitted over the second line of the first serial bus and the second line of the second serial bus in accordance with timing provided by a clock signal transmitted over the first line of the first serial bus.

公开(公告)号：US20220358079A1

公开(公告)日：2022-11-10

申请号：US17307842

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Sharon GRAIF ,  Lior AMARILIO ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

公开(公告)号：US20220107912A1

公开(公告)日：2022-04-07

申请号：US17061357

申请日：2020-10-01

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic WIETFELDT ,  Lalan Jee MISHRA ,  Radu PITIGOI-ARON

IPC: G06F13/42

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals and control messages over a serial communication link. An apparatus includes a serial bus, and a controller configured to represent a series of signaling state of physical general-purpose input/output (GPIO) in a batch that comprises a sequence of virtual GPIO messages and control messages, generate a first header that includes timing information configured to control timing of execution of the batch, transmit the first header over a communication link, and transmit the batch over the communication link.