公开(公告)号：US10140044B2

公开(公告)日：2018-11-27

申请号：US15086943

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Priyankar Mathuria ,  Rakesh Kumar Sinha ,  Gururaj Shamanna

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/419

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a memory. The memory may include a first memory portion configured to store a first bit and generate a first data bit output. The first data bit output may be a function of the first bit when a first read enable is active. The memory may also include a second memory portion configured to store a second bit and generate a second data bit output. The second data bit output may be a function of the second bit when a second read enable is active. The memory may include a switch configured to select between the first and second bits for a read operation based on the first and second data bit outputs.

公开(公告)号：US09030863B2

公开(公告)日：2015-05-12

申请号：US14038434

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C8/14 ,  H01L27/1104 ,  H01L27/1116

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract translation: 集成电路包括一个或多个位单元，耦合到所述一个或多个位单元的字线以及与所述字线布置以在其间具有电容的虚拟字线。 该电容提供了字线的升压或降压以辅助读和写操作。

公开(公告)号：US10147483B1

公开(公告)日：2018-12-04

申请号：US15708818

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Mukund Narasimhan ,  Rakesh Kumar Sinha ,  Raghav Gupta

IPC: G11C11/00 ,  G11C11/419

Abstract: Systems, methods, and apparatus for writing data into a static random access memory (SRAM) are provided. A write driver circuit includes a bitcell array, a bitline coupled to the bitcell array, and a first driving circuit configured to drive the bitline via a write driver node for writing data into a bitcell for a write operation. The write driver circuit also includes a pre-charging circuit configured to control or to operate with the write driver circuit to drive the write driver node to a high voltage level or a low voltage level for the write operation, and pre-charge the write driver node to the high voltage level, and float the write driver node for a bit-masking operation.

公开(公告)号：US09837144B1

公开(公告)日：2017-12-05

申请号：US15408086

申请日：2017-01-17

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Mukund Narasimhan ,  Sharad Kumar Gupta

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1009 ,  G11C7/1096 ,  G11C7/12

Abstract: A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.