公开(公告)号：US10147483B1

公开(公告)日：2018-12-04

申请号：US15708818

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Mukund Narasimhan ,  Rakesh Kumar Sinha ,  Raghav Gupta

IPC: G11C11/00 ,  G11C11/419

Abstract: Systems, methods, and apparatus for writing data into a static random access memory (SRAM) are provided. A write driver circuit includes a bitcell array, a bitline coupled to the bitcell array, and a first driving circuit configured to drive the bitline via a write driver node for writing data into a bitcell for a write operation. The write driver circuit also includes a pre-charging circuit configured to control or to operate with the write driver circuit to drive the write driver node to a high voltage level or a low voltage level for the write operation, and pre-charge the write driver node to the high voltage level, and float the write driver node for a bit-masking operation.

公开(公告)号：US09865337B1

公开(公告)日：2018-01-09

申请号：US15466749

申请日：2017-03-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mukund Narasimhan ,  Raghav Gupta ,  Pradeep Raj ,  Rahul Sahu ,  Po-Hung Chen ,  Chulmin Jung

IPC: G11C5/10 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/417

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.