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    Memory timing circuit
    11.
    发明授权
    Memory timing circuit 有权
    存储器定时电路

    公开(公告)号：US09111589B2

    公开(公告)日：2015-08-18

    申请号：US14018404

    申请日：2013-09-04

    Applicant: QUALCOMM Incorporated

    Inventor： Rakesh Kumar Sinha ,  Chirag Gulati ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/22

    CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

    Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

    Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。

    Weak keeper circuit for memory device
    12.
    发明授权
    Weak keeper circuit for memory device 有权
    存储器件弱保护电路

    公开(公告)号：US09082465B2

    公开(公告)日：2015-07-14

    申请号：US13765533

    申请日：2013-02-12

    Applicant: QUALCOMM Incorporated

    Inventor： Balachander Ganesan ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18

    CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/18

    Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.

    Abstract translation: 提供一种存储器电路，其包括耦合到位线的多个位单元，其允许访问来自多个位单元中的每一个的信息。 感测反相器耦合到位线的输出端。 保持器电路具有耦合到位线的输出以补偿来自多个位单元的电流泄漏。 保持器电路可以包括与p沟道金属氧化物 - 硅（PMOS）晶体管串联的n沟道金属氧化物 - 硅（NMOS）晶体管。

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