公开(公告)号：US20210263720A1

公开(公告)日：2021-08-26

申请号：US16798887

申请日：2020-02-24

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth Boenapalli ,  Sai Praneeth Sreeram ,  Surendra Paravada ,  Venu Madhav Mokkapati

IPC: G06F8/65 ,  G06F11/07 ,  G06F11/10 ,  G06F3/06 ,  G11C11/4076

Abstract: Systems and methods for flash memory conflict avoidance cause a firmware over the air (FOTA) update to be given priority over a scrubbing operation unless the memory element meets or exceeds a predefined health degradation parameter. When the memory element meets or exceeds the predefined health degradation parameter, the scrubbing operation is given priority over the FOTA update. By enforcing these priorities, scrubbing and FOTA updates do not occur at the same time and conflicts are thereby avoided. Since conflicts are avoided, the chance of memory corruption is decreased and the chance of “bricking” the computing device is likewise decreased.

公开(公告)号：US11048438B2

公开(公告)日：2021-06-29

申请号：US16400468

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth Boenapalli ,  Sai Praneeth Sreeram ,  Surendra Paravada ,  Venu Madhav Mokkapati

IPC: G06F3/00 ,  G06F3/06

Abstract: In some aspects, the present disclosure provides a method for managing data communication rates of a memory device. The method includes receiving an input/output (I/O) operation to be performed by the memory device, detecting a temperature of the memory device, and determining whether the detected temperature satisfies a threshold condition. The threshold condition is satisfied if the detected temperature is above a first temperature threshold or below a second temperature threshold. If the threshold condition is satisfied, selecting a gear from a plurality of gears based on a ranking of the plurality of gears at the detected temperature, wherein each gear of the plurality of gears correspond to a respective one of a plurality of data rates used by the memory device for performing I/O operations, and serving, to the memory device, the I/O operation with an indication to perform the I/O operation using the selected gear.

公开(公告)号：US10410730B1

公开(公告)日：2019-09-10

申请号：US15942380

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth Boenapalli ,  Surendra Paravada ,  Sai Praneeth Sreeram ,  Venu Madhav Mokkapati

IPC: G06F12/00 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/32 ,  G06F12/02

Abstract: An embodiment is directed to an apparatus that comprises a host controller and a flash memory. The host controller monitors a temperature in a first memory block of the flash memory (e.g., based on a reported temperature measurements from the flash memory), and selectively synchronizes a first refresh of the first memory block with a second refresh of a second memory block of the flash memory based in part upon the monitored temperature. For example, an immediate refresh of the first memory block may be performed if there is a pending I/O request for the first memory block, an error rate associated with the first memory block exceeds an error rate threshold and/or the monitored temperature of the first memory block exceeds a temperature threshold; otherwise, a synchronized refresh of the first and second memory blocks may be executed.

公开(公告)号：US12298912B1

公开(公告)日：2025-05-13

申请号：US18509066

申请日：2023-11-14

Applicant: QUALCOMM Incorporated

Inventor： Rajesh Kumar Biswal ,  Manmeet Singh Ahluwalia ,  Surendra Paravada ,  Madhu Yashwanth Boenapalli ,  Sai Praneeth Sreeram

IPC: G06F12/0891 ,  G06F12/02

Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

公开(公告)号：US12197775B2

公开(公告)日：2025-01-14

申请号：US18189141

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy Akavaram ,  Sonali Jabreva ,  Prakhar Srivastava ,  Surendra Paravada ,  Yogananda Rao Chillariga ,  Madhu Yashwanth Boenapalli

IPC: G06F3/06

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

公开(公告)号：US11800342B2

公开(公告)日：2023-10-24

申请号：US17448195

申请日：2021-09-20

Applicant: QUALCOMM Incorporated

Inventor： Sai Praneeth Sreeram ,  Surendra Paravada ,  Madhu Yashwanth Boenapalli ,  Bipul Tarafdar

IPC: H04W4/90 ,  G06V40/12 ,  G06V40/13 ,  G06F3/048

CPC classification number: H04W4/90 ,  G06F3/048 ,  G06V40/1306 ,  G06V40/1365

Abstract: A method may involve receiving fingerprint sensor data from a fingerprint sensor system, detecting, according to the fingerprint sensor data, a presence of a digit on an outer surface of the apparatus in a fingerprint sensor system area; determining, according to the fingerprint sensor data, a digit force or a digit pressure of the digit on the outer surface of the apparatus; and making, according to the fingerprint sensor data, a time threshold determination. The time threshold determination may involve determining whether a length of time during which the digit force exceeds a threshold digit force or during which the digit pressure exceeds a threshold digit pressure is greater than or equal to a threshold length of time. The method may involve determining, based at least in part on the time threshold determination, whether to enable one or more emergency response functions of the apparatus.

公开(公告)号：US11275620B2

公开(公告)日：2022-03-15

申请号：US16824338

申请日：2020-03-19

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth Boenapalli ,  Surendra Paravada ,  Sai Praneeth Sreeram

IPC: G06F12/02 ,  G06F3/06 ,  G06F9/50 ,  G06F9/54 ,  G06F9/30 ,  G06F11/34 ,  G06F12/123 ,  G06F9/46

Abstract: A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.

公开(公告)号：US10078611B1

公开(公告)日：2018-09-18

申请号：US15626544

申请日：2017-06-19

Applicant: QUALCOMM Incorporated

Inventor： Surendra Paravada ,  Madhu Yashwanth Boenapalli ,  Venu Madhav Mokkapati

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/28 ,  G06F13/20

CPC classification number: G06F13/409 ,  G06F13/20 ,  G06F13/28

Abstract: Aspects include computing devices and methods implemented by computing devices for smart of handling input/output interrupts associated with device setting levels. Various aspects may include receiving a hardware input/output interrupt from a hardware interface, updating an adjusted feature setting level, determining whether the adjusted feature setting level equals a feature setting level limit, and changing an interrupt service routine address stored at a first location of a hardware input/output register corresponding with an interrupt service routine associated with the hardware input/output interrupt to a first data in response to determining that the adjusted feature setting level of the computing device equals the adjusted feature setting level limit.