公开(公告)号：US20240250009A1

公开(公告)日：2024-07-25

申请号：US18158225

申请日：2023-01-23

Applicant: QUALCOMM Incorporated

Inventor： Seongryul Choi ,  Joan Rey Villarba Buot ,  Kuiwon Kang ,  Zhijie Wang

IPC: H01L23/498 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/288 ,  H01L21/76829 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/08112 ,  H01L2224/08225 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48225

Abstract: Embedded trace substrates (ETS) having an ETS metallization layer with T-shaped interconnects with reduced-width embedded metal traces, and related integrated circuit (IC) packages and fabrication methods. The ETS includes an outer ETS metallization layer that includes T-shaped interconnects for supporting input/output (I/O) connections between the ETS and another opposing package substrate. To increase density of I/O interconnections, the pitch of the embedded metal traces in the ETS metallization layer is reduced. The T-shaped interconnects also each include an additional metal contact pad that is coupled to a respective embedded metal trace to increase the height of the embedded metal trace to eliminate a vertical connection gap between the ETS and an opposing package substrate. In the T-shape interconnects, their embedded metal traces are reduced in width in a horizontal direction(s) as compared to their respective metal contact pads to provide room for additional metal traces for additional signal routing capacity.

公开(公告)号：US11562962B2

公开(公告)日：2023-01-24

申请号：US17148367

申请日：2021-01-13

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

Abstract: A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.

公开(公告)号：US11289453B2

公开(公告)日：2022-03-29

申请号：US16803804

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: A package comprising a substrate, an integrated device, and an interconnect structure. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing at least one electrical connection to a board. The integrated device is coupled to the first surface of the substrate. The interconnect structure is coupled to the first surface of the substrate. The integrated device, the interconnect structure and the substrate are coupled together in such a way that when a first electrical signal travels between the integrated device and the board, the first electrical signal travels through at least the substrate, then through the interconnect structure and back through the substrate.

公开(公告)号：US10679919B2

公开(公告)日：2020-06-09

申请号：US16016888

申请日：2018-06-25

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Zhijie Wang ,  Bohan Yan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.