公开(公告)号：US20240104034A1

公开(公告)日：2024-03-28

申请号：US18348534

申请日：2023-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Rajesh GHIMIRE

IPC: G06F13/28 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F13/28 ,  G06T1/20 ,  G06T1/60

Abstract: A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.

公开(公告)号：US20230162315A1

公开(公告)日：2023-05-25

申请号：US17531302

申请日：2021-11-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

IPC: G06T1/20 ,  G06T7/11 ,  G06T3/40 ,  G06T1/00

CPC classification number: G06T1/20 ,  G06T7/11 ,  G06T3/4015 ,  G06T1/0007

Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

公开(公告)号：US20230162013A1

公开(公告)日：2023-05-25

申请号：US17954831

申请日：2022-09-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Manabu KOIKE

IPC: G06N3/063 ,  G06F5/01 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/5443

Abstract: A semiconductor device according to one embodiment executes a neural network processing. A first shift register sequentially generates a plurality of pieces of quantized input data by quantizing a plurality of pieces of output data sequentially inputted from a first buffer by bit-shifting. A product-sum operator generates operation data by performing a product-sum operation to a plurality of parameters and the plurality of pieces of quantized input data from the first shift register. The second shift register generates the output data by inversely quantizing the operation data from the product-sum operator by bit-shifting, and stores the output data in the first buffer.

公开(公告)号：US20210349819A1

公开(公告)日：2021-11-11

申请号：US16868041

申请日：2020-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NAKAMURA ,  Akihiro YAMAMOTO ,  Kazuaki TERASHIMA ,  Manabu KOIKE

IPC: G06F12/06 ,  G06F12/02 ,  G06F9/48 ,  G06F9/30 ,  G06F9/52 ,  G06F13/16 ,  G11C11/408

Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.

公开(公告)号：US20180150386A1

公开(公告)日：2018-05-31

申请号：US15792480

申请日：2017-10-24

Applicant: Renesas Electronics Corporation

Inventor： Motoyasu TAKABATAKE ,  Hisashi SHIOTA ,  Atsushi NAKAMURA ,  Yuji CHIBA

IPC: G06F11/36

CPC classification number: G06F11/3612 ,  G06F11/362

Abstract: The size of a multi-processor is prevented from increasing even when the number of processor cores is increased. The multi-processor includes a plurality of cores and a debugging control unit. At least one of the plurality of cores is a debugging core, the debugging core being connected to the debugging control unit so that the debugging control unit can refer to and update register information in the debugging core. The debugging control unit transfers register information in a first core to the debugging core, the first core being one of the plurality of cores and being a core to be debugged. The debugging core debugs a program by using the transferred register information, the program being to be executed in the first core.

公开(公告)号：US20170310356A1

公开(公告)日：2017-10-26

申请号：US15649275

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NAKAMURA ,  Masahiro TOYAMA ,  Masafumi WATANABE ,  Kota TOIDA ,  Aya OHMAE ,  Wen LI

IPC: H04B1/7073 ,  H04B15/04

CPC classification number: H04B1/7073 ,  H04B15/04

Abstract: A clock control circuit includes a clock controller which disperses a harmonic of a clock signal in a used frequency band of a reception signal and controls an amplitude of a harmonic remaining in the used frequency band after the dispersion on a basis of a spread frequency used for the dispersion and a spread width of the harmonic.

公开(公告)号：US20160062812A1

公开(公告)日：2016-03-03

申请号：US14825739

申请日：2015-08-13

Applicant: Renesas Electronics Corporation

Inventor： Motoyasu TAKABATAKE ,  Akihiro YAMAMOTO ,  Atsushi NAKAMURA

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0706 ,  G06F11/22

Abstract: The execution time of a self diagnosis program is reduced. A compiler apparatus includes: a specify unit that specifies, out of a plurality of resources included in a diagnosis target apparatus, a use resource group being a set of resources used by an instruction string included in an object program executed on the diagnosis target apparatus; a determine unit that determines, in accordance with the specified use resource group, a target resource group being a set of resources to be targets of a self diagnosis in the diagnosis target apparatus; and an output unit that outputs, for causing the self diagnosis on the determined target resource group to be executed in the diagnosis target apparatus, information based on the target resource group to the diagnosis target apparatus.

Abstract translation: 减少自诊断程序的执行时间。 编译装置包括：指定单元，其从包括在诊断对象装置中的多个资源中指定使用资源组，所述资源组是由在所述诊断对象装置上执行的对象程序中包含的指示串使用的资源集合; 确定单元，其根据所述指定的使用资源组，确定作为所述诊断对象装置中的自身目标的资源的一组资源组; 以及输出单元，其输出用于使所述确定的目标资源组上的自诊断在所述诊断对象装置中执行的信息，基于所述目标资源组到所述诊断对象装置。

公开(公告)号：US20130182747A1

公开(公告)日：2013-07-18

申请号：US13739997

申请日：2013-01-11

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NAKAMURA ,  Masahiro TOYAMA ,  Masafumi WATANABE ,  Kota TOIDA ,  Aya OHMAE ,  Wen LI

IPC: H04B1/7073

CPC classification number: H04B1/7073 ,  H04B15/04

Abstract: To provide a clock control circuit, a demodulation device, and a spread spectrum method, which can reduce interference caused by a clock signal on which spread spectrum is performed when demodulating a signal. A clock controller 22 according to the present invention disperses a harmonic of a clock signal in a used frequency band of a reception signal and controls a harmonic remaining in the used frequency band after the dispersion. For example, the clock controller 22 controls an amplitude of the harmonic on the basis of a spread frequency used for the dispersion and a spread width of the harmonic.

Abstract translation: 提供时钟控制电路，解调装置和扩展频谱方法，其可以在解调信号时减少由扩频进行时钟信号引起的干扰。 根据本发明的时钟控制器22将时钟信号的谐波分散在接收信号的使用频带中，并且控制在分散之后所使用的频带中剩余的谐波。 例如，时钟控制器22基于用于色散的扩展频率和谐波的扩展宽度来控制谐波的幅度。