公开(公告)号：US20250159363A1

公开(公告)日：2025-05-15

申请号：US18925421

申请日：2024-10-24

Applicant: Renesas Electronics Corporation

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI

IPC: H04N23/80 ,  H04N23/60

Abstract: A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.

公开(公告)号：US20220398441A1

公开(公告)日：2022-12-15

申请号：US17345368

申请日：2021-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

IPC: G06N3/063 ,  G06F13/20 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: A semiconductor device executes the processing of a neural network. The memory MEM1 holds a plurality of pixel values and j compressed weighting factors. The decompressor DCMP restores the j compressed weighting factors to the uncompressed k (k≥j) weighting factors. The DMA controller DMAC1 reads the j compressed weighting factors from the memory MEM1 and transfers them to the decompressor DCMP. The n (n>k) accumulators in the accumulator unit ACCU multiply a plurality of pixel values and k uncompressed weighting factor to accumulate and add the multiplication results to the time series. A switch circuit SW1 provided between the decompressor DCMP and the accumulator unit ACCU transfers the k uncompressed weighting factors restored by the decompressor DCMP to n accumulators based on the correspondence represented by the identifier.

公开(公告)号：US20230162315A1

公开(公告)日：2023-05-25

申请号：US17531302

申请日：2021-11-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

IPC: G06T1/20 ,  G06T7/11 ,  G06T3/40 ,  G06T1/00

CPC classification number: G06T1/20 ,  G06T7/11 ,  G06T3/4015 ,  G06T1/0007

Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

公开(公告)号：US20240348939A1

公开(公告)日：2024-10-17

申请号：US18623841

申请日：2024-04-01

Applicant: Renesas Electronics Corporation

Inventor： Isao NAGAYOSHI ,  Kazuaki TERASHIMA

IPC: H04N23/80 ,  H04N23/84

CPC classification number: H04N23/80 ,  H04N23/843

Abstract: A semiconductor device or image processing system includes n interface circuit and a channel composite circuit. The interface circuit outputs a first packet including the line data of the k-th line included in the image data of the first channel, and then outputs a second packet including the line data of the k-th line included in the image data of the second channel. The channel combination circuit writes, to the memory, the line data of the k-th line included in the image data of the first channel to the first address area, and then writes the line data of the k-th line included in the image data of the second channel to the second address area that is consecutive to the first address area.

公开(公告)号：US20240054083A1

公开(公告)日：2024-02-15

申请号：US18336215

申请日：2023-06-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

IPC: G06F13/16 ,  G06F13/28 ,  G06F7/544

CPC classification number: G06F13/1673 ,  G06F13/28 ,  G06F7/5443

Abstract: A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.

公开(公告)号：US20160180918A1

公开(公告)日：2016-06-23

申请号：US14977232

申请日：2015-12-21

Applicant: Renesas Electronics Corporation

Inventor： Isao NAGAYOSHI

IPC: G11C11/406 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1636 ,  G11C7/1018 ,  G11C7/1072

Abstract: A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.

Abstract translation: 根据实施例的半导体器件（100）根据确定结果计算地址集（A）的突发存取次数，对于N个地址a1至an（N为自然数，不小于 两个）包括在地址集（A）中，无论访问顺序中的该地址与该地址相邻的地址是否可以被相同的突发访问访问，并且计算将用于访问地址集的访问时间 通过突发访问。