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公开(公告)号：US08185879B2
公开(公告)日：2012-05-22
申请号：US11557005
申请日：2006-11-06
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.
摘要翻译： 用于跟踪多任务嵌入式流水线处理器的方法包括执行包括跟踪控制的编译代码。 执行编译代码时启动跟踪。 编译代码的执行完成后，跟踪停止。 在跟踪期间形成跟踪记录。 跟踪记录包括处理器模式指示，应用空间标识值和指令体系结构设置模式指示。
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公开(公告)号：US07043668B1
公开(公告)日：2006-05-09
申请号：US09894830
申请日：2001-06-29
IPC分类号： G06F11/32
CPC分类号： G06F11/3636
摘要： A system and method for program counter and data tracing is disclosed. Generated trace messages are included within a trace word format and stored in trace memory, thereby enabling a reduction in the amount of trace storage required.
摘要翻译： 公开了一种用于程序计数器和数据跟踪的系统和方法。 生成的跟踪消息包含在跟踪字格式中，并存储在跟踪存储器中，从而可以减少所需的跟踪存储量。
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公开(公告)号：US20070180333A1
公开(公告)日：2007-08-02
申请号：US11557005
申请日：2006-11-06
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
摘要翻译： 公开了一种用于程序计数器和数据跟踪的系统和方法。 本发明的跟踪机制能够增强对处理器核心的硬件和软件状态的可见性。
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公开(公告)号：US07065675B1
公开(公告)日：2006-06-20
申请号：US09850195
申请日：2001-05-08
IPC分类号： G06F11/00
CPC分类号： G01R31/318544 , G01R31/31705
摘要： A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.
摘要翻译： 通过测试访问端口提供有效的块传输操作的系统和方法使用Fastdata寄存器。 Fastdata寄存器部分地模拟通常在与测试访问端口相关联的控制寄存器中找到的待处理进程访问位（“PrAcc”）。 当FastData访问（Fastdata上传或Fastdata下载）被耦合到测试访问端口的探测器请求时，Fastdata寄存器串行耦合到也与测试访问端口相关联的数据寄存器。 通过这些寄存器如此耦合，并通过Fastdata寄存器的操作，可以使用单个寄存器操作来完成下载和上传数据。
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公开(公告)号：US20070192567A1
公开(公告)日：2007-08-16
申请号：US11674924
申请日：2007-02-14
申请人： Lawrence Hudepohl , Darren Jones , Radhika Thekkath , Franz Treue
发明人： Lawrence Hudepohl , Darren Jones , Radhika Thekkath , Franz Treue
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.
摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。
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公开(公告)号：US07194599B2
公开(公告)日：2007-03-20
申请号：US11380925
申请日：2006-04-29
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.
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公开(公告)号：US20060259738A1
公开(公告)日：2006-11-16
申请号：US11380925
申请日：2006-04-29
申请人： Lawrence Hudepohl , Darren Jones , Radhika Thekkath , Franz Treue
发明人： Lawrence Hudepohl , Darren Jones , Radhika Thekkath , Franz Treue
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.
摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。
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公开(公告)号：US07134116B1
公开(公告)日：2006-11-07
申请号：US09844668
申请日：2001-04-30
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
摘要翻译： 公开了一种用于程序计数器和数据跟踪的系统和方法。 本发明的跟踪机制能够提高对处理器核心的硬件和软件状态的可见性。
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公开(公告)号：US20050038975A1
公开(公告)日：2005-02-17
申请号：US10923584
申请日：2004-08-21
申请人： Lawrence Hudepohl , Darren Jones , Radhika Thekkath , Franz Treue
发明人： Lawrence Hudepohl , Darren Jones , Radhika Thekkath , Franz Treue
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.
摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。
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20.发明授权公开(公告)号：US08433072B2
公开(公告)日：2013-04-30
申请号：US12743211
申请日：2008-11-07
CPC分类号： H04R25/658 , H04R25/305 , H04R25/604 , H04R25/70 , H04R2420/05
摘要： The invention regards a hearing aid comprising a receiver and a signal processing device, wherein the signal processing device is electrically coupled to a connection socket operable to detachably connect the receiver to the socket and whereby the signal processing device further comprise a detector operable to detect a characteristics of the receiver which is connected to the signal processing device through the connection socket. The present invention addresses the problem of identification of individual receiver properties as well as of identifying different types of receivers.
摘要翻译： 本发明涉及一种包括接收器和信号处理装置的助听器，其中信号处理装置电耦合到可操作以将接收器可拆卸地连接到插座的连接插座，由此信号处理装置还包括可操作以检测 通过连接插座连接到信号处理装置的接收器的特性。 本发明解决了识别各个接收机属性以及识别不同类型的接收机的问题。
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