公开(公告)号：US09136733B2

公开(公告)日：2015-09-15

申请号：US13167250

申请日：2011-06-23

Applicant: Rajesh Narwal ,  Shantanu Goel

Inventor： Rajesh Narwal ,  Shantanu Goel

IPC: H02J1/00 ,  H02J3/00 ,  H02J9/06 ,  G06F1/04 ,  G06F1/26 ,  H02M1/14

CPC classification number: H02J9/061 ,  G06F1/04 ,  G06F1/26 ,  H02J2009/068 ,  H02M1/14 ,  Y10T307/696

Abstract: A system switches between application of a first supply voltage and a second supply voltage to a load. The second supply voltage is a regulated voltage that is generated from the first supply voltage, or is alternatively generated from a reference voltage, such as bandgap. When the load is supplied from the first supply voltage, the regulated voltage is also generated from the first supply voltage. At or after switching the load to the second supply voltage, the regulated voltage is generated instead from the reference voltage. The load is a clock circuit, such as an oscillator. The controlled switching of the supply voltage for the load in the manner described addresses concerns over introducing errors in the output clock signal when the clock circuit's supply voltage is changed.

Abstract translation: 系统在向负载施加第一电源电压和第二电源电压之间切换。 第二电源电压是从第一电源电压产生的调节电压，或者是替代地从参考电压（例如带隙）产生的。 当从第一电源电压提供负载时，也从第一电源电压产生调节电压。 在将负载切换到第二电源电压之后或之后，产生调节电压而不是参考电压。 负载是时钟电路，例如振荡器。 以所述方式控制负载的电源电压切换解决了当时钟电路的电源电压改变时引入输出时钟信号中的误差的问题。

公开(公告)号：US08502559B2

公开(公告)日：2013-08-06

申请号：US13298389

申请日：2011-11-17

Applicant: Rajesh Narwal

Inventor： Rajesh Narwal

IPC: H03L5/00 ,  H03K19/0175

CPC classification number: H03K19/018521

Abstract: A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.

Abstract translation: 电路具有被配置为接收具有第一值的周期性信号的输入。 当所述周期信号具有上升沿时，提供第一电路以产生脉冲，当所述周期信号具有下降沿时，提供脉冲。 第二电路被配置为接收所述脉冲并响应于此提供输出信号，所述输出信号具有与所述输入信号相同的占空比并且具有第二值。

公开(公告)号：US20130127514A1

公开(公告)日：2013-05-23

申请号：US13298389

申请日：2011-11-17

Applicant: Rajesh Narwal

Inventor： Rajesh Narwal

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.

Abstract translation: 电路具有被配置为接收具有第一值的周期性信号的输入。 当所述周期信号具有上升沿时，提供第一电路以产生脉冲，当所述周期信号具有下降沿时，提供脉冲。 第二电路被配置为接收所述脉冲并响应于此提供输出信号，所述输出信号具有与所述输入信号相同的占空比并且具有第二值。

公开(公告)号：US06856179B2

公开(公告)日：2005-02-15

申请号：US10662952

申请日：2003-09-12

Applicant: Rajesh Kaushik ,  Rajesh Narwal

Inventor： Rajesh Kaushik ,  Rajesh Narwal

IPC: H03K17/16 ,  H03K3/00

CPC classification number: H03K17/166

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract translation: CMOS输出缓冲器使用来自接地节点的反馈，通过利用可容忍的接地反弹限制来减少接地反弹，使其对工作条件和处理参数的敏感性降低。 输出缓冲器的NMOS器件的输入由从接地节点接收来自预驱动器的第一输入和第二输入（即，反馈）的控制元件的输出提供。