公开(公告)号：US20120326517A1

公开(公告)日：2012-12-27

申请号：US13167250

申请日：2011-06-23

Applicant: Rajesh Narwal ,  Shantanu Goel

Inventor： Rajesh Narwal ,  Shantanu Goel

IPC: H02J1/00

CPC classification number: H02J9/061 ,  G06F1/04 ,  G06F1/26 ,  H02J2009/068 ,  H02M1/14 ,  Y10T307/696

Abstract: A system switches between application of a first supply voltage and a second supply voltage to a load. The second supply voltage is a regulated voltage that is generated from the first supply voltage, or is alternatively generated from a reference voltage, such as bandgap. When the load is supplied from the first supply voltage, the regulated voltage is also generated from the first supply voltage. At or after switching the load to the second supply voltage, the regulated voltage is generated instead from the reference voltage. The load is a clock circuit, such as an oscillator. The controlled switching of the supply voltage for the load in the manner described addresses concerns over introducing errors in the output clock signal when the clock circuit's supply voltage is changed.

Abstract translation: 系统在向负载施加第一电源电压和第二电源电压之间切换。 第二电源电压是从第一电源电压产生的调节电压，或者是替代地从参考电压（例如带隙）产生的。 当从第一电源电压提供负载时，也从第一电源电压产生调节电压。 在将负载切换到第二电源电压之后或之后，产生调节电压而不是参考电压。 负载是时钟电路，例如振荡器。 以所述方式控制负载的电源电压切换解决了当时钟电路的电源电压改变时引入输出时钟信号中的误差的问题。

公开(公告)号：US09136733B2

公开(公告)日：2015-09-15

申请号：US13167250

申请日：2011-06-23

Applicant: Rajesh Narwal ,  Shantanu Goel

Inventor： Rajesh Narwal ,  Shantanu Goel

IPC: H02J1/00 ,  H02J3/00 ,  H02J9/06 ,  G06F1/04 ,  G06F1/26 ,  H02M1/14

CPC classification number: H02J9/061 ,  G06F1/04 ,  G06F1/26 ,  H02J2009/068 ,  H02M1/14 ,  Y10T307/696

Abstract: A system switches between application of a first supply voltage and a second supply voltage to a load. The second supply voltage is a regulated voltage that is generated from the first supply voltage, or is alternatively generated from a reference voltage, such as bandgap. When the load is supplied from the first supply voltage, the regulated voltage is also generated from the first supply voltage. At or after switching the load to the second supply voltage, the regulated voltage is generated instead from the reference voltage. The load is a clock circuit, such as an oscillator. The controlled switching of the supply voltage for the load in the manner described addresses concerns over introducing errors in the output clock signal when the clock circuit's supply voltage is changed.

Abstract translation: 系统在向负载施加第一电源电压和第二电源电压之间切换。 第二电源电压是从第一电源电压产生的调节电压，或者是替代地从参考电压（例如带隙）产生的。 当从第一电源电压提供负载时，也从第一电源电压产生调节电压。 在将负载切换到第二电源电压之后或之后，产生调节电压而不是参考电压。 负载是时钟电路，例如振荡器。 以所述方式控制负载的电源电压切换解决了当时钟电路的电源电压改变时引入输出时钟信号中的误差的问题。

公开(公告)号：US20070170955A1

公开(公告)日：2007-07-26

申请号：US11615680

申请日：2006-12-22

Applicant: Rajesh Narwal ,  Manoj Kumar

Inventor： Rajesh Narwal ,  Manoj Kumar

IPC: H03K19/094

CPC classification number: H03K19/00315

Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

Abstract translation: 高耐压输出缓冲器使用衬底电压控制电路来控制输出缓冲器中的晶体管的衬底上的电压。 输出缓冲器的电路使得任何晶体管的任何两个端子之间的电压不允许超过输出缓冲器的电源电压。 同时，输出缓冲器的晶体管的源极或漏极的电压不允许超过其衬底电压。 所提出的用于输出缓冲器的电路可以容忍高于其工作电压的电压。 新颖的电路使用更少的硬件并防止电路中的功耗。

公开(公告)号：US20050184782A1

公开(公告)日：2005-08-25

申请号：US11018275

申请日：2004-12-21

Applicant: Manoj Sharma ,  Sunil Kasanyal ,  Rajesh Narwal

Inventor： Manoj Sharma ,  Sunil Kasanyal ,  Rajesh Narwal

IPC: H03K3/3565 ,  H03K5/08 ,  H04L25/02 ,  H03K3/037

CPC classification number: H04L25/0292 ,  H03K3/3565 ,  H03K5/084 ,  H04L25/0272

Abstract: The differential input receiver provides constant symmetrical hysteresis over a wide input signal range. The differential input receiver includes a pair of complementary differential comparators having common input terminals, a pair of series connected complementary current mirrors each having source terminals driven by the output terminals of the corresponding differential comparator, a pair of transistors connected in series across each differential pair transistor in each differential comparator to form a potential divider across it, and a pair of series connected inverting buffers connected to a common output of the differential comparators to provide the final output. The individual buffer outputs are fed back to the control terminals of the series connected transistors in a manner that provides positive feedback thereby providing equal rise-time, fall-delay and transition times in the output signal.

Abstract translation: 差分输入接收器在宽输入信号范围内提供恒定的对称滞后。 差分输入接收机包括一对具有公共输入端的互补差分比较器，一对串联连接的互补电流镜，每个具有由相应的差分比较器的输出端驱动的源极端子，一对晶体管串联连接在每个差分对上 晶体管在每个差分比较器中形成分压器，并且一对串联连接的反相缓冲器连接到差分比较器的公共输出端以提供最终输出。 单个缓冲器输出以提供正反馈的方式反馈到串联连接的晶体管的控制端，从而在输出信号中提供相等的上升时间，下降延迟和转换时间。

公开(公告)号：US20070188193A1

公开(公告)日：2007-08-16

申请号：US11649746

申请日：2007-01-03

Applicant: Rajesh Narwal ,  Manoj Kumar

Inventor： Rajesh Narwal ,  Manoj Kumar

IPC: H03K19/0175

CPC classification number: H03K19/018528

Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Abstract translation: 提出了一种低电平到高电平转换器的实施例。 该转换器将芯的低电压摆幅信号转换为I / O块的高电压摆幅信号。 这种转换器对于核心和I / O电源电压差异非常大的高速应用尤其有用，例如，核心工作在0.8V，I / O工作在3.6V或更高，而没有 很少或没有静态功耗。 与传统的翻译器相比，所提出的翻译器可以提供改进的转换时间和传播延迟。 与其他这样的翻译器相比，所提出的翻译器也可以使用较少的硬件。

公开(公告)号：US06903576B2

公开(公告)日：2005-06-07

申请号：US10675923

申请日：2003-09-29

Applicant: Rajesh Narwal

Inventor： Rajesh Narwal

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/0175

CPC classification number: H03K3/356165 ,  H03K3/012 ,  H03K3/356113

Abstract: An improved low voltage to high voltage translator for digital electronic circuits providing reduced rise times, fall times and transition times that remain independent of operating conditions. This is accomplished by modifying a conventional low-to-high voltage translator to include a switched active pull-up at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the output from the low-to-high-voltage translator and a switched active pull-down at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the complement of the output from the low-to-high-voltage translator, so as at to provide regenerative pull-up and pull-down that also counteracts the bootstrap capacitance at the output of the first high-voltage switch.

Abstract translation: 用于数字电子电路的改进的低电压至高电压转换器，其提供保持独立于操作条件的上升时间，下降时间和转换时间。 这是通过修改常规的低到高电压转换器来实现的，以在第一高压开关的输出处包括由输入低电压信号控制并由低电压信号的输出门控的开关有源上拉， 高电压转换器和第一高压开关输出端的开关有源下拉，由输入低电压信号控制，并由低电压转换器输出的补码门控 ，以便提供也抵抗第一高压开关输出端的自举电容的再生上拉和下拉。

公开(公告)号：US07999573B2

公开(公告)日：2011-08-16

申请号：US11649746

申请日：2007-01-03

Applicant: Rajesh Narwal ,  Manoj Kumar

Inventor： Rajesh Narwal ,  Manoj Kumar

IPC: H03K19/094

CPC classification number: H03K19/018528

Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Abstract translation: 提出了一种低电平到高电平转换器的实施例。 该转换器将芯的低电压摆幅信号转换为I / O块的高电压摆幅信号。 这种转换器对于核心和I / O电源电压差异非常大的高速应用尤其有用，例如，核心工作在0.8V，I / O工作在3.6V或更高，而没有 很少或没有静态功耗。 与传统的翻译器相比，所提出的翻译器可以提供改进的转换时间和传播延迟。 与其他这样的翻译器相比，所提出的翻译器也可以使用较少的硬件。

公开(公告)号：US07394291B2

公开(公告)日：2008-07-01

申请号：US11615680

申请日：2006-12-22

Applicant: Rajesh Narwal ,  Manoj Kumar

Inventor： Rajesh Narwal ,  Manoj Kumar

IPC: H03K19/0175

CPC classification number: H03K19/00315

Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

Abstract translation: 高耐压输出缓冲器使用衬底电压控制电路来控制输出缓冲器中的晶体管的衬底上的电压。 输出缓冲器的电路使得任何晶体管的任何两个端子之间的电压不允许超过输出缓冲器的电源电压。 同时，输出缓冲器的晶体管的源极或漏极的电压不允许超过其衬底电压。 所提出的用于输出缓冲器的电路可以容忍高于其工作电压的电压。 新颖的电路使用更少的硬件并防止电路中的功耗。

公开(公告)号：US20160060344A1

公开(公告)日：2016-03-03

申请号：US14838650

申请日：2015-08-28

Applicant: Rajesh Narwal ,  Marlon C. Rebelatto ,  Keith Steele ,  Paul Robbins ,  Ross Anthony Stewart ,  John A. Blake-Haskins ,  Joyson J. Karakunnel ,  Ramy Ibrahim ,  Aiman Shalabi ,  Alessandra Di Pietro ,  Li Shi ,  Shengyan Hong ,  Paul Stockman ,  Marc Ballas ,  Mohammed M. Dar

Inventor： Rajesh Narwal ,  Marlon C. Rebelatto ,  Keith Steele ,  Paul Robbins ,  Ross Anthony Stewart ,  John A. Blake-Haskins ,  Joyson J. Karakunnel ,  Ramy Ibrahim ,  Aiman Shalabi ,  Alessandra Di Pietro ,  Li Shi ,  Shengyan Hong ,  Paul Stockman ,  Marc Ballas ,  Mohammed M. Dar

IPC: C07K16/28

CPC classification number: C07K16/2827 ,  A61K2039/505 ,  A61K2039/507 ,  A61K2039/545 ,  C07K16/2818 ,  C07K2317/21 ,  C07K2317/76

Abstract: The present invention features methods of treating lung cancer (e.g., NSCLC) with an anti-PD-L1 antibody and tremelimumab in a subject identified as having a PD-L1 negative tumor.

Abstract translation: 本发明的特征在于鉴定为具有PD-L1阴性肿瘤的受试者中具有抗PD-L1抗体和tremeimumab治疗肺癌（例如NSCLC）的方法。

公开(公告)号：US06879198B2

公开(公告)日：2005-04-12

申请号：US10739879

申请日：2003-12-18

Applicant: Manoj Kumar ,  Rajesh Narwal

Inventor： Manoj Kumar ,  Rajesh Narwal

IPC: H03K3/3565 ,  H03K3/037

CPC classification number: H03K3/3565

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract translation: 具有参考电压两侧的迟滞的差分输入接收器可以包括双输入单输出差分放大器，其包括连接在一起的共同端子的两个输入晶体管。 每个晶体管的控制端可以连接到差分放大器的一个输入端。 差分放大器的输出可以连接到一组级联的数字反相器/缓冲器，并且每个数字缓冲器的输出可以连接到反馈晶体管的控制端子。 反馈晶体管可以并联连接在每个输入晶体管上，使得当一个输入电压在第二输入处增加到或低于第二输入处的输入电压以下预定阈值时，反馈晶体管操作以提供正反馈以促进快速 在输出端切换动作。