公开(公告)号：US20080273403A1

公开(公告)日：2008-11-06

申请号：US12125011

申请日：2008-05-21

申请人： Sebastian Ehrenreich ,  Jente B. Kuang ,  Chun-Tao Li ,  Hung Cai Ngo

发明人： Sebastian Ehrenreich ,  Jente B. Kuang ,  Chun-Tao Li ,  Hung Cai Ngo

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50012

摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

摘要翻译： 包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。 存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。 访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。 测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。 多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

公开(公告)号：US07408829B2

公开(公告)日：2008-08-05

申请号：US11352699

申请日：2006-02-13

申请人： Jente B. Kuang ,  Hung Cai Ngo

发明人： Jente B. Kuang ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

摘要翻译： 本文提供了为集成电路配置电源管理系统的方法和布置。 功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。 集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。 这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。 这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

公开(公告)号：US20080130387A1

公开(公告)日：2008-06-05

申请号：US11741187

申请日：2007-04-27

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50012 ,  G11C2029/1204

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。 驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作 。 该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。 弱写入条件和/或弱写入条件可以通过选择性加载来测量。

公开(公告)号：US07835212B2

公开(公告)日：2010-11-16

申请号：US12099913

申请日：2008-04-09

申请人： Jente B. Kuang ,  Hung Cai Ngo

发明人： Jente B. Kuang ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

摘要翻译： 本文提供了为集成电路配置电源管理系统的方法和布置。 功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。 集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。 这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。 这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

公开(公告)号：US20090016141A1

公开(公告)日：2009-01-15

申请号：US12099913

申请日：2008-04-09

申请人： Jente B. Kuang ,  Hung Cai Ngo

发明人： Jente B. Kuang ,  Hung Cai Ngo

IPC分类号： G05F1/10 ,  G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

摘要翻译： 本文提供了为集成电路配置电源管理系统的方法和布置。 功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。 集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。 这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。 这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

公开(公告)号：US07349271B2

公开(公告)日：2008-03-25

申请号：US11250061

申请日：2005-10-13

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50012 ,  G11C2029/1204

摘要： A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

摘要翻译： 具有用于评估存储器单元性能的位线驱动装置的级联测试电路在实际存储器电路环境中提供电路延迟和性能测量。 存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。 驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作 。 该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者可以响应于级联头部引入的转换来测量级联的延迟。 弱写入条件和/或弱写入条件可以通过选择性加载来测量。

公开(公告)号：US07266707B2

公开(公告)日：2007-09-04

申请号：US10942419

申请日：2004-09-16

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

IPC分类号： G06F1/00

CPC分类号： G06F1/3228

摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

摘要翻译： 低功耗流水线电路架构具有电源分配管线级。 第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。 电源门控第二管道级具有两个电源门控模式。 通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。 在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。 在第二电源门控模式下，电源轨与第一电压电位分离。 电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。 第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。

公开(公告)号：US07864625B2

公开(公告)日：2011-01-04

申请号：US12244286

申请日：2008-10-02

申请人： Gary D. Carpenter ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

发明人： Gary D. Carpenter ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

IPC分类号： G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C7/22 ,  G11C11/419

摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.

摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。

公开(公告)号：US07847618B2

公开(公告)日：2010-12-07

申请号：US11970771

申请日：2008-01-08

申请人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

发明人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

IPC分类号： H03K3/01

CPC分类号： H02M3/073 ,  H02M2003/077 ,  H03L5/00

摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

公开(公告)号：US20100220541A1

公开(公告)日：2010-09-02

申请号：US12778960

申请日：2010-05-12

申请人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

发明人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

IPC分类号： G11C5/14 ,  G05F3/02

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C11/4074 ,  G11C2207/104

摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.

摘要翻译： 开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。 电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。 提供负电荷泵和正电荷泵实施例。 充电电路有利地利用非重叠的宽和窄的时钟信号来产生多个门控信号。 泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。 可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。