公开(公告)号：US07266707B2

公开(公告)日：2007-09-04

申请号：US10942419

申请日：2004-09-16

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

IPC分类号： G06F1/00

CPC分类号： G06F1/3228

摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

摘要翻译： 低功耗流水线电路架构具有电源分配管线级。 第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。 电源门控第二管道级具有两个电源门控模式。 通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。 在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。 在第二电源门控模式下，电源轨与第一电压电位分离。 电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。 第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。

公开(公告)号：US06975134B2

公开(公告)日：2005-12-13

申请号：US10821048

申请日：2004-04-08

申请人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H03K19/017

CPC分类号： H03K19/00361 ,  H03K19/0016 ,  H03K19/01721

摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

摘要翻译： 具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。 第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。 第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。 每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。 第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。 当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。 缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。

公开(公告)号：US20120212997A1

公开(公告)日：2012-08-23

申请号：US13459932

申请日：2012-04-30

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US20080155362A1

公开(公告)日：2008-06-26

申请号：US11552158

申请日：2006-10-24

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US07276932B2

公开(公告)日：2007-10-02

申请号：US10926597

申请日：2004-08-26

申请人： Jente B. Kuang ,  Jethro C. Law ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jethro C. Law ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： H03K19/23

CPC分类号： H03K19/0016

摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.

摘要翻译： 虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。 每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。 在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。 控制信号在单元边界被锁存或响应于时钟信号锁存。

公开(公告)号：US06980018B2

公开(公告)日：2005-12-27

申请号：US10835501

申请日：2004-04-29

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/094

CPC分类号： H03K19/01721 ,  H03K19/00361

摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.

摘要翻译： 具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。 第一个逻辑路径由小型设备组成，并配置为提供缓冲区的逻辑功能，无需驱动大负载。 第二和第三逻辑路径具有直到最后一个反相级的第一逻辑路径的逻辑功能。 每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。 第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。 当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。 缓冲器可以是逆变器，非逆变器，或提供多输入逻辑功能。

公开(公告)号：US08555119B2

公开(公告)日：2013-10-08

申请号：US13459932

申请日：2012-04-30

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US08261138B2

公开(公告)日：2012-09-04

申请号：US11552158

申请日：2006-10-24

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US07760565B2

公开(公告)日：2010-07-20

申请号：US11781994

申请日：2007-07-24

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung C. Ngo ,  Kevin J. Nowka ,  Liang-Teck Pang ,  Jayakumaran Sivagnaname

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung C. Ngo ,  Kevin J. Nowka ,  Liang-Teck Pang ,  Jayakumaran Sivagnaname

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G01R31/31937 ,  G11C29/50012 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.

摘要翻译： 用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。 存储阵列的列以环形连接，形成环形振荡器。 每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。 环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。 该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。

公开(公告)号：US07061265B2

公开(公告)日：2006-06-13

申请号：US10916980

申请日：2004-08-12

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

IPC分类号： H03K19/03

CPC分类号： H03K17/167 ,  H03K19/0016

摘要： Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials of the power supply from circuitry with large high leakage devices. Driver circuits comprise a low leakage logic path for holding logic states of the output. A high leakage logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each high leakage path that enhances the current drive of a logic state on the output are leakage stress relieved by allowing their drive inputs to collapse after the output logic state has been asserted. The high leakage logic paths employ multiple stages with collapsing logic states that are generated in response to asserted logic states on the output and logic states of the low leakage logic path thus reducing the device sizes needed to control leakage.