公开(公告)号：US6075387A

公开(公告)日：2000-06-13

申请号：US54591

申请日：1998-04-03

Applicant: Ralph Urbansky

Inventor： Ralph Urbansky

IPC: H03D13/00 ,  H03L7/085 ,  H04J3/16 ,  H04L7/033

CPC classification number: H04J3/1611 ,  H03L7/085 ,  H04L7/033 ,  H03D13/004

Abstract: The invention relates to a phase detector, especially for a Phase Locked Loop of a desynchronizer of a digital transmission system for the transmission of signals of the synchronous digital hierarchy with a difference former (subtractor) connected to a comparator, to which can be conducted at the input side, via a first accumulator, a first input signal, and via a second accumulator a second input signal with the comparator being connected at the output side via a coder to a control input of the second accumulator.

Abstract translation: 本发明涉及一种相位检测器，特别是用于数字传输系统的去同步器的锁相环，用于通过连接到比较器的差分变换器（减法器）传输同步数字层级的信号，其可以在 所述输入侧经由第一累加器，第一输入信号，以及经由第二累加器，所述比较器的输出端经由编码器连接到所述第二累加器的控制输入端的第二输入信号。

公开(公告)号：US5859882A

公开(公告)日：1999-01-12

申请号：US541384

申请日：1995-10-10

Applicant: Ralph Urbansky

Inventor： Ralph Urbansky

IPC: H04J3/00 ,  H04J3/07 ,  H04L7/00 ,  H04L7/033 ,  H03L7/087

CPC classification number: H04J3/076

Abstract: The invention relates to a transmission system comprising a control circuit which circuit includes a comparator (18, 19, 20; 25 to 29; 46; 50 to 52, 57 to 60) for comparing a first input signal and a second input signal. For reducing the low-frequency phase error, the comparator (18, 19, 20; 25 to 29; 46; 50 to 52, 57 to 60) is provided for changing the state of a first comparing signal derived from the first input signal and/or the state of a second comparing signal derived from the second input signal, or the state of the output signal resulting from a combination of the two comparing signals at instants denoted by an auxiliary signal whose frequency deviates from the frequency of the signal to be changed.

Abstract translation: 本发明涉及一种包括控制电路的传输系统，该控制电路包括用于比较第一输入信号和第二输入信号的比较器（18,19,20; 25至29; 46; 50至52,57至60）。 为了降低低频相位误差，提供比较器（18,19,20; 25至29; 46; 50至52,57至60），用于改变从第一输入信号导出的第一比较信号的状态，以及 /或从第二输入信号导出的第二比较信号的状态，或由频率偏离信号频率的辅助信号所表示的两个比较信号的组合产生的输出信号的状态 改变了

公开(公告)号：US5550876A

公开(公告)日：1996-08-27

申请号：US296210

申请日：1994-08-25

Applicant: Ralph Urbansky

Inventor： Ralph Urbansky

IPC: H04J3/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/14 ,  H04J3/16 ,  H04L7/00

CPC classification number: H04J3/076 ,  H04J3/14 ,  H04J3/1611

Abstract: The invention relates to a measuring device for measuring the phase deviation of at least a subordinate transport unit of a synchronous signal transmitted through a synchronous transmission system. The measuring device comprises a transmitter unit for forming the synchronous signal to be transmitted, a first desynchronizer for splitting up the synchronous signal and for detecting at least a given byte of the subordinate transport unit, a second desynchronizer for splitting up the received synchronous signal which has passed through the transmission system and for detecting at least the given byte in the received synchronous signal, and an evaluation unit for calculating the phase deviation from the moments of detection of at least the given byte in the transmitted and the received synchronous signals.

Abstract translation: 本发明涉及一种用于测量通过同步传输系统传输的同步信号的至少下级传输单元的相位偏差的测量装置。 测量装置包括用于形成要发射的同步信号的发射机单元，用于分离同步信号并用于检测至少下位传输单元的给定字节的第一去同步器，用于分离所接收的同步信号的第二去同步器， 已经通过传输系统并且用于检测所接收的同步信号中的给定字节，以及评估单元，用于从至少发送的给定字节和接收到的同步信号的检测时刻计算相位偏差。

公开(公告)号：US5359605A

公开(公告)日：1994-10-25

申请号：US167432

申请日：1993-12-13

Applicant: Ralph Urbansky ,  Michael Niegel ,  Miguel Robledo

Inventor： Ralph Urbansky ,  Michael Niegel ,  Miguel Robledo

IPC: H04J3/07 ,  H04J3/06

CPC classification number: H04J3/076

Abstract: A circuit for adjusting the bit rates of two signals is necessary for plesiochronous multiplexers, for example, to bring the plesiochronous signals, which are to be combined to one digital signal of the next higher hierarchy, to the same bit rate. For this purpose, the circuit arrangement comprises an elastic store (4) as well as a justification decision circuit (15, 16). In order that a circuit having such features can be used for bit rates of the order of 140 Mbit/s and yet can be arranged largely in CMOS technology, the bit clocks of the first and second signals are reduced at the ratio of 1:n. Furthermore, a serial-to-parallel converter (2) converts bit groups of n serial bits of a first signal into bit groups of n parallel bits, which are written in groups into the elastic store (4) and are also read out in groups. The parallel bit groups read out are applied to a controllable selection matrix (5) having n outputs, which transmits n selected bits of more than one bit group to n outputs. The justification decision circuit (15, 16) controls the reading operation of the elastic store (4) and also the selection matrix (5).

Abstract translation: 用于调整两个信号的比特率的电路对于同步多路复用器是必要的，例如，将要组合到下一较高层的一个数字信号的同步信号到相同的比特率。 为此，电路装置包括弹性存储器（4）以及校准判定电路（15,16）。 为了具有这样的特征的电路可以用于140Mbit / s量级的比特率，并且可以大量地在CMOS技术中被布置，第一和第二信号的比特时钟以1：n的比率被减少 。 此外，串行到并行转换器（2）将第一信号的n个串行比特的比特组转换成n个并行比特的组，它们被分组地写入到弹性存储器（4）中，并且也被分组读出 。 读出的并行比特组被应用于具有n个输出的可控选择矩阵（5），其将n个选择的多个比特组的比特发送到n个输出。 理由判定电路（15,16）控制弹性存储器（4）的读取操作以及选择矩阵（5）。

公开(公告)号：US5263056A

公开(公告)日：1993-11-16

申请号：US751365

申请日：1991-08-29

Applicant: Ralph Urbansky

Inventor： Ralph Urbansky

IPC: H04L7/00 ,  H04J3/06 ,  H04L25/36

CPC classification number: H04J3/0623

Abstract: A single signal is formed from two plesiochronous signals. The first signal's data are written in parallel in groups of n bits each. Writing and reading are controlled by respective counters, whose counts are also provided to a subtractor. A control loop for bit rate justification is formed by the subtractor, a controller and the read counter. A track counter counts the stuffed bits modulo n, and stops the read counter for one clock period after each n stuffed bits. The mean value of the subtractor output and the count of the track counter are set off against each other, and their result is used for justification formation and a preparation signal for incrementing the track counter.

Abstract translation: 单个信号由两个准同步信号形成。 第一个信号的数据被并行写入，每组n位。 写入和读取由相应的计数器控制，其计数也提供给减法器。 比特率调整的控制环由减法器，控制器和读取计数器形成。 轨道计数器对填充比特模数n进行计数，并在每个n个填充比特之后停止一个时钟周期的读取计数器。 减法器输出的平均值和轨道计数器的计数相互抵消，其结果用于调整形成和用于递增轨道计数器的准备信号。

公开(公告)号：US5132970A

公开(公告)日：1992-07-21

申请号：US549345

申请日：1990-07-06

Applicant: Ralph Urbansky

Inventor： Ralph Urbansky

IPC: H04L7/00 ,  H04J3/07

CPC classification number: H04J3/076

Abstract: A circuit arrangement for adapting the bit rates of two signals includes an elastic store into which the data of the first signal are written in parallel in groups of n bits and from which the data bits of the second signal are read out in parallel. A selection matrix for inserting justification bits in the second signal is connected to the output of the elastic store. Writing into the store is controlled by a write counter and read-out therefrom into the selection matrix is controlled by a read counter. A subtractor forms the difference between the counts. A justification decision circuit, which can be realized all or part in CMOS technology and is capable of bit rates of the order of 140 Mbits per second, is connected to the subtractor and the read counter so as to form a control loop for the elastic store. The justification decision circuit includes a controller which produces an output signal corresponding to a running integrated summation of the differences produced by the subtractor, and a pulse distribution circuit. The output signal of the controller controls the pulse distribution circuit to supply pulses which cause the selection matrix to insert justification bits, and cause the read counter to compensate for a difference in the bit rates of the first and second signals.

Abstract translation: 用于适应两个信号的比特率的电路装置包括弹性存储器，第一信号的数据以n位组并行写入到其中，并且从其并行地读出第二信号的数据位。 用于在第二信号中插入对齐位的选择矩阵连接到弹性存储器的输出。 写入存储器的写入由计数器控制，并且从读出计数器控制读取到选择矩阵中。 减法器形成计数之间的差异。 可以实现全部或部分在CMOS技术中并且能够将每秒140Mbits的比特率实现的理由判定电路连接到减法器和读取计数器，以形成用于弹性存储器的控制环路 。 理由判定电路包括：控制器，其产生与由减法器产生的差异的运行累加求和相对应的输出信号;以及脉冲分配电路。 控制器的输出信号控制脉冲分配电路以提供使选择矩阵插入对齐位的脉冲，并使读计数器补偿第一和第二信号的比特率的差异。