Program memory source switching for high speed and/or low power program execution in a digital processor
    11.
    发明申请
    Program memory source switching for high speed and/or low power program execution in a digital processor 审中-公开
    程序存储器源切换,用于在数字处理器中执行高速和/或低功耗程序

    公开(公告)号:US20070094454A1

    公开(公告)日:2007-04-26

    申请号:US11254373

    申请日:2005-10-20

    CPC classification number: G06F12/06 G06F12/0638 Y02D10/13

    Abstract: An integrated circuit digital processor is coupled to either a main program memory or a secondary program memory, wherein the secondary program memory may be low power, high reliability, non-volatile and/or fast memory that may store a limited number of critical program instructions and data for execution by the digital processor. A program memory switch may couple the digital processor to either the main program memory or the secondary program memory. This is particularly advantageous in that the secondary program memory may have attributes not economically feasible with the main program memory. A program memory controller may handle the selection of which of these memories that the digital processor is using to obtain its program instructions, and necessary control signals for switching and operation thereof.

    Abstract translation: 集成电路数字处理器耦合到主程序存储器或辅助程序存储器,其中次要程序存储器可以是可以存储有限数量的关键程序指令的低功率,高可靠性,非易失性和/或快速存储器 以及由数字处理器执行的数据。 程序存储器开关可以将数字处理器耦合到主程序存储器或辅助程序存储器。 这是特别有利的,因为次程序存储器可能具有在主程序存储器中经济可行的属性。 程序存储器控制器可以处理数字处理器正在使用的这些存储器中的哪一个的选择以获得其程序指令,以及用于其切换和操作的必要控制信号。

    Programmable selective wake-up for radio frequency transponder
    12.
    发明申请
    Programmable selective wake-up for radio frequency transponder 审中-公开
    射频应答器的可编程选择性唤醒

    公开(公告)号:US20050237161A1

    公开(公告)日:2005-10-27

    申请号:US11079878

    申请日:2005-03-14

    Abstract: A remote keyless entry (RKE) transponder has a programmable selective wake-up filter for determining whether the RKE transponder should wake-up to process a received signal. The wake-up filter correlates the timing of an input signal's carrier amplitude on and off time periods to a predefined programmable time period profile for a desired signal which has a certain carrier on time (time period on) and a certain carrier off time (time period off) arranged into a coded “header.” When a received signal matches the predefined time period profile, then the RKE transponder will wake-up to process the incoming signal data. The predefined time period profile may be programmable and may be stored in a header configuration register. Each RKE transponder has unique predefined time period on and time period off profiles.

    Abstract translation: 远程无钥匙进入(RKE)转发器具有可编程选择性唤醒滤波器,用于确定RKE应答器是否应该被唤醒以处理接收到的信号。 唤醒滤波器将输入信号的载波幅度开和关时间周期的定时与预定的可编程时间段分布相关联,用于对于具有一定载波的时间(时间周期)和某个载波关闭时间(时间周期)的期望信号 期间关闭)排列成编码“标题”。 当接收到的信号与预定义的时间段曲线匹配时,则RKE应答器将被唤醒以处理输入的信号数据。 预定义的时间段简档可以是可编程的,并且可以存储在头部配置寄存器中。 每个RKE转发器具有独特的预定义时间段和时间段关闭配置文件。

    Low capacitance ESD-protection structure under a bond pad
    13.
    发明申请
    Low capacitance ESD-protection structure under a bond pad 有权
    焊接垫下的低电容ESD保护结构

    公开(公告)号:US20050189593A1

    公开(公告)日:2005-09-01

    申请号:US10787387

    申请日:2004-02-26

    Applicant: Randy Yach

    Inventor: Randy Yach

    CPC classification number: H01L27/0259 Y10S257/917

    Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure comprises adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer located between the bond pad and the P+ and N+ diffusions. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N− well is located substantially under the N+ and P+ diffusions. The surrounding N+ diffusion partially overlaps the edge of the N− well below it. An outer portion of the N+ diffusion, the portion overlapping the N− well, is within a P− well. The P− well may be the substrate of the integrated circuit. Another N+ diffusion encircles the N+ diffusion surrounding the P+ diffusions. The another N+ diffusion is in the P− well and a field oxide may be located between the N+ diffusion and the another N+ diffusion. An NPN field transistor is formed with the N+ diffusion being the transistor collector, the P− well being the transistor base and the another N+ diffusion being the emitter. The another N+ diffusion (emitter) may be connected to ground by a conductive connection, e.g., metal or low resistance semiconductor material.

    Abstract translation: ESD保护结构基本上位于集成电路接合焊盘下方。 该ESD保护结构通过在接合焊盘和ESD钳位电路之间插入正向二极管而形成为低电容结构。 将ESD保护结构放在接合焊盘下方可消除寄生衬底电容,并利用由插入的正向偏置二极管形成的寄生PNP晶体管。 ESD保护结构包括相邻的交替的P +和N +扩散,其基本上位于接合焊盘下面以被ESD保护。 P +扩散通过位于接合焊盘和P +和N +扩散之间的绝缘层与金属通孔连接到接合焊盘金属。 N +扩散与P +扩散相邻。 N +扩散围绕N +和P +扩散,并将N +扩散结合在一起,以便在每个P +扩散周围完全形成连续的N +扩散。 N阱基本上位于N +和P +扩散之下。 周围的N +扩散与其下面的N阱的边缘部分重叠。 N +扩散的外部部分,与N阱重叠的部分在P-阱内。 P-阱可以是集成电路的衬底。 另外N +扩散围绕围绕P +扩散的N +扩散。 另一个N +扩散在P-阱中,场氧化物可以位于N +扩散与另一个N +扩散之间。 形成NPN场晶体管,其中N +扩散为晶体管集电极,P阱为晶体管基极,另一N +扩散为发射极。 另一个N +扩散(发射极)可以通过导电连接(例如金属或低电阻半导体材料)连接到地。

    Method and apparatus for monitoring via's in a semiconductor fab
    14.
    发明授权
    Method and apparatus for monitoring via's in a semiconductor fab 有权
    用于在半导体晶圆厂中监测通孔的方法和装置

    公开(公告)号:US07919973B2

    公开(公告)日:2011-04-05

    申请号:US12128403

    申请日:2008-05-28

    Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

    Abstract translation: 用于监测半导体制造工艺的方法产生半导体芯片晶片。 每个芯片都有一个或多个二极管。 每个二极管可寻址作为阵列的一部分,对应于芯片的物理位置,并且串联连接到堆叠。 堆叠由一个更多的垂直互连和金属触点组成。 寻址二极管和相关联的垂直互连堆栈,并测量通过阵列中的每个垂直互连堆叠的电流。

    High voltage ESD-protection structure

    公开(公告)号:US20050247980A1

    公开(公告)日:2005-11-10

    申请号:US11183640

    申请日:2005-07-18

    CPC classification number: H01L27/0259

    Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

    Programmable selective wake-up for radio frequency transponder
    17.
    发明授权
    Programmable selective wake-up for radio frequency transponder 有权
    射频应答器的可编程选择性唤醒

    公开(公告)号:US08164416B2

    公开(公告)日:2012-04-24

    申请号:US12490545

    申请日:2009-06-24

    Abstract: A remote keyless entry (RKE) transponder has a programmable selective wake-up filter for determining whether the RKE transponder should wake-up to process a received signal. The wake-up filter correlates the timing of an input signal's carrier amplitude on and off time periods to a predefined programmable time period profile for a desired signal which has a certain carrier on time (time period on) and a certain carrier off time (time period off) arranged into a coded “header.” When a received signal matches the predefined time period profile, then the RKE transponder will wake-up to process the incoming signal data. The predefined time period profile may be programmable and may be stored in a header configuration register. Each RKE transponder has unique predefined time period on and time period off profiles.

    Abstract translation: 远程无钥匙进入(RKE)转发器具有可编程选择性唤醒滤波器,用于确定RKE应答器是否应该被唤醒以处理接收到的信号。 唤醒滤波器将输入信号的载波幅度开和关时间周期的定时与预定的可编程时间段分布相关联,用于对于具有一定载波的时间(时间周期)和某个载波关闭时间(时间周期)的期望信号 周期关闭),当接收到的信号与预定义的时间段配置文件匹配时,RKE应答器将被唤醒以处理输入的信号数据。 预定义的时间段简档可以是可编程的,并且可以存储在头部配置寄存器中。 每个RKE转发器具有独特的预定义时间段和时间段关闭配置文件。

    METHOD AND APPARATUS FOR MONITORING VIA'S IN A SEMICONDUCTOR FAB
    19.
    发明申请
    METHOD AND APPARATUS FOR MONITORING VIA'S IN A SEMICONDUCTOR FAB 有权
    用于通过SEMICONDUCTOR FAB监测的方法和装置

    公开(公告)号:US20110140728A1

    公开(公告)日:2011-06-16

    申请号:US13033792

    申请日:2011-02-24

    Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

    Abstract translation: 用于监测半导体制造工艺的方法产生半导体芯片晶片。 每个芯片都有一个或多个二极管。 每个二极管可寻址作为阵列的一部分,对应于芯片的物理位置,并且串联连接到堆叠。 堆叠由一个更多的垂直互连和金属触点组成。 寻址二极管和相关联的垂直互连堆栈,并测量通过阵列中的每个垂直互连堆叠的电流。

    Constant Current Output Sink or Source
    20.
    发明申请
    Constant Current Output Sink or Source 有权
    恒流输出槽或源

    公开(公告)号:US20100148700A1

    公开(公告)日:2010-06-17

    申请号:US12622745

    申请日:2009-11-20

    CPC classification number: H05B33/0806 H05B33/0815

    Abstract: A constant current output sink or source eliminates a current limiting series resistor for a light emitting diode (LED) and maintains a constant light intensity from the LED for all operating and manufacturing variables of a digital device since the current through the LED is maintained at a constant value. The constant current output sink or source may be programmable for selection of a constant current value from a plurality of constant current values available.

    Abstract translation: 恒定电流输出接收器或源极消除了用于发光二极管(LED)的限流串联电阻器,并且为了数字器件的所有操作和制造变量而保持来自LED的恒定的光强度,因为通过LED的电流维持在 恒定值。 恒流输出接收器或源可以是可编程的,用于从可用的多个恒定电流值中选择恒定电流值。

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