公开(公告)号：US11362190B2

公开(公告)日：2022-06-14

申请号：US16881412

申请日：2020-05-22

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Brian D. Schultz ,  John Logan ,  Robert E. Leoni ,  Nicholas J. Kolias

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/47

Abstract: A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.

公开(公告)号：US20210351288A1

公开(公告)日：2021-11-11

申请号：US17380379

申请日：2021-07-20

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Brian D. Schultz ,  John Logan ,  Christos Thomidis

IPC: H01L29/778 ,  H01L21/223 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

公开(公告)号：US11127596B2

公开(公告)日：2021-09-21

申请号：US16322731

申请日：2017-08-02

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Brian D. Schultz ,  Amanda Kerr

IPC: H01L21/02 ,  H01L21/265 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/36 ,  H01L29/207

Abstract: A method includes providing a single crystal substrate having a buffer layer on a surface of the substrate. The buffer layer provides a transition between the crystallographic lattice structure of the substrate and the crystallographic lattice structure of the semiconductor layer and has its resistivity increased by ion implanting a dopant into the buffer layer; and forming semiconductor layer on the ion implanted buffer layer. The semiconductor layer may be a wide bandgap semiconductor layer having a high electron mobility transistors formed therein.

公开(公告)号：US11101378B2

公开(公告)日：2021-08-24

申请号：US16379077

申请日：2019-04-09

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Brian D. Schultz ,  John Logan ,  Christos Thomidis

IPC: H01L29/778 ,  H01L21/223 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

公开(公告)号：US20210202729A1

公开(公告)日：2021-07-01

申请号：US16727252

申请日：2019-12-26

Applicant: Raytheon Company

Inventor： Abbas Torabi ,  Brian D. Schultz ,  John Logan

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A High Electron Mobility Transistor structure having: a GaN buffer layer disposed on the substrate; a doped GaN layer disposed on, and in direct contact with, the buffer layer, such doped GaN layer being doped with more than one different dopants; an unintentionally doped (UID) GaN channel layer on, and in direct contact with, the doped GaN layer, such UID GaN channel layer having a 2DEG channel therein; a barrier layer on, and in direct contact with, the UID GaN channel layer. One of the dopants is beryllium and another one of the dopants is carbon.

公开(公告)号：US20200328296A1

公开(公告)日：2020-10-15

申请号：US16379077

申请日：2019-04-09

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Brian D. Schultz ,  John Logan ,  Christos Thomidis

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66 ,  H01L21/223

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

公开(公告)号：US20170250273A1

公开(公告)日：2017-08-31

申请号：US15052977

申请日：2016-02-25

Applicant: Raytheon Company

Inventor： Brian D. Schultz ,  Eduardo M. Chumbes

IPC: H01L29/778 ,  H01L29/205

CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/207

Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.

公开(公告)号：US09419125B1

公开(公告)日：2016-08-16

申请号：US14740703

申请日：2015-06-16

Applicant: Raytheon Company

Inventor： Brian D. Schultz ,  Abbas Torabi ,  Eduardo M. Chumbes ,  Shahed Reza ,  William E. Hoke

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/0254 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/36 ,  H01L29/7781 ,  H01L29/7786

Abstract: A semiconductor structure having a Group III-N buffer layer and a Group III-N barrier layer in direct contact to form a junction between the Group III-V buffer layer the Group III-N barrier layer producing a two dimensional electron gas (2DEG) channel, the Group III-N barrier layer having a varying dopant concentration. The lower region of the Group III-N barrier layer closest to the junction is void of intentionally introduced dopant and a region above the lower region having intentionally introduced, predetermined dopant with a predetermined doping concentration above 1×1017 atoms per cm3.

Abstract translation: 具有直接接触的III-N族缓冲层和III-N族阻挡层的半导体结构，以形成产生二维电子气（2DEG）的III-V族阻挡层的III-V族缓冲层之间的结， 通道，具有改变掺杂剂浓度的III-N族阻挡层。 最接近结的III-N族阻挡层的下部区域没有有意引入的掺杂剂和有意引入预定掺杂剂的下部区域上方的区域，其预定掺杂浓度高于1×1017原子/ cm3。