公开(公告)号：US07491985B2

公开(公告)日：2009-02-17

申请号：US11288843

申请日：2005-11-29

申请人： Peter J. Geiss ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu

发明人： Peter J. Geiss ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

摘要翻译： 提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。 具体地，本发明的HBT包括至少包括子集电极的基板; 位于子集电极上的埋置难熔金属硅化物层; 以及位于掩埋难熔金属硅化物层的表面上的浅沟槽隔离区域。 本发明还提供一种制造这种HBT的方法。 该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

公开(公告)号：US07002190B1

公开(公告)日：2006-02-21

申请号：US10711479

申请日：2004-09-21

申请人： Peter J. Geiss ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu

发明人： Peter J. Geiss ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

公开(公告)号：US07709338B2

公开(公告)日：2010-05-04

申请号：US11614757

申请日：2006-12-21

申请人： Qizhi Liu ,  Peter B. Gray ,  Alvin J. Joseph

发明人： Qizhi Liu ,  Peter B. Gray ,  Alvin J. Joseph

IPC分类号： H01L21/331

CPC分类号： H01L29/41708 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371

摘要： A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction.

摘要翻译： 在双极互补金属氧化物半导体（BiCMOS）工艺中制造异质结双极晶体管（HBT）结构的方法在未被临时发射极和间隔物覆盖的区域中的基极区域上选择性地增厚氧化物层，使得临时 可以去除发射极，并且可以暴露基极 - 发射极结，而不会完全去除覆盖在未被临时发射极或间隔物覆盖的基极区域的区域上的氧化物。 结果，不需要光掩模去除临时发射体并露出基极 - 发射极结。

公开(公告)号：US07265010B2

公开(公告)日：2007-09-04

申请号：US10863630

申请日：2004-06-08

申请人： Peter B. Gray ,  Jeffrey B. Johnson

发明人： Peter B. Gray ,  Jeffrey B. Johnson

IPC分类号： H01L21/8238

CPC分类号： H01L27/0826 ,  H01L21/82285 ,  Y10S438/969

摘要： The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.

摘要翻译： 本发明包括用于制造用于BiCMOS器件的高性能垂直NPN和PNP晶体管的方法和结果。 所产生的高性能垂直PNP晶体管包括包括硅和锗的发射极区域，并且其PNP发射极与NPN晶体管的基极共享单层硅。 该方法为CMOS和双极器件的常规制造工艺增加了两个附加的掩模步骤，因此代表了整个工艺流程的微小添加。 所得到的结构显着增强了PNP器件的性能。

公开(公告)号：US06670255B2

公开(公告)日：2003-12-30

申请号：US09965289

申请日：2001-09-27

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Peter B. Gray ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Peter B. Gray ,  Anthony K. Stamper

IPC分类号： H01L21331

CPC分类号： H01L27/1203 ,  H01L27/0664

摘要： Disclosed is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.

摘要翻译： 公开了一种制造横向半导体器件的方法，包括：提供衬底，至少具有在衬底的上部中至少形成至少一个第一掺杂剂型区域和至少一个第二掺杂剂类型区域的上硅部分，至少 第一掺杂剂类型区域中的一个与第二掺杂剂类型区域中的至少一个邻接，从而形成至少一个PN结; 以及在所述上硅部分的顶表面上形成至少一个保护岛，所述保护岛延伸所述PN结的长度并与所述第一掺杂剂型区域的一部分和邻接的第二掺杂剂型区域的一部分重叠。

公开(公告)号：US07972919B2

公开(公告)日：2011-07-05

申请号：US11160956

申请日：2005-07-18

申请人： Peter B. Gray ,  Benjamin T. Voegeli

发明人： Peter B. Gray ,  Benjamin T. Voegeli

IPC分类号： H01L21/8234

CPC分类号： H01L29/7378 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/66242 ,  Y10S438/969

摘要： The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.

摘要翻译： 本发明涉及一种位于半导体衬底中并包含高性能垂直NPN和PNP晶体管的器件结构。 具体地，垂直PNP晶体管具有发射极区域，垂直NPN晶体管具有本征基极区域。 垂直PNP晶体管的发射极区域和垂直NPN晶体管的本征基极区域位于单个含硅锗层中，并且它们都包含单晶硅锗。 本发明还涉及一种用于制造这种基于用于CMOS和双极器件的传统制造工艺的侧面修改的器件结构的方法，其中很少或没有附加的处理步骤。

公开(公告)号：US08389372B2

公开(公告)日：2013-03-05

申请号：US12951516

申请日：2010-11-22

申请人： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

发明人： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

公开(公告)号：US07214593B2

公开(公告)日：2007-05-08

申请号：US09773798

申请日：2001-02-01

申请人： Douglas Duane Coolbaugh ,  Peter B. Gray ,  Donna Kaye Johnson ,  Michael Joseph Zierak

发明人： Douglas Duane Coolbaugh ,  Peter B. Gray ,  Donna Kaye Johnson ,  Michael Joseph Zierak

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitter prior to siliciding the structure. The presence of the passivation layer in the structure prevents silicide shorts from occurring by eliminating bridging between adjacent silicide regions; therefore improved SiGe bipolar yield is obtained. A method for forming such a structure is also provided.

摘要翻译： SiGe异质结双极晶体管至少包括形成在SiGe基极区上的发射极，其中发射极的侧壁由保形钝化层保护。 在将结构硅化之前，在所述发射体的暴露的侧壁上形成共形钝化层。 该结构中钝化层的存在通过消除相邻硅化物区域之间的桥接来防止发生硅化物短路; 因此获得了改善的SiGe双极产率。 还提供了一种用于形成这种结构的方法。

公开(公告)号：US06909164B2

公开(公告)日：2005-06-21

申请号：US10065837

申请日：2002-11-25

申请人： Peter B. Gray ,  Jeffrey B. Johnson

发明人： Peter B. Gray ,  Jeffrey B. Johnson

IPC分类号： H01L21/336 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/082 ,  H01L27/102 ,  H01L27/108 ,  H01L29/12 ,  H01L29/70 ,  H01L29/732 ,  H01L31/11

CPC分类号： H01L27/0826 ,  H01L21/82285 ,  Y10S438/969

摘要： The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.

摘要翻译： 本发明包括用于制造用于BiCMOS器件的高性能垂直NPN和PNP晶体管的方法和结果。 所产生的高性能垂直PNP晶体管包括包括硅和锗的发射极区域，并且其PNP发射极与NPN晶体管的基极共享单层硅。 该方法为CMOS和双极器件的常规制造工艺增加了两个附加的掩模步骤，因此代表了整个工艺流程的微小添加。 所得到的结构显着增强了PNP器件的性能。

公开(公告)号：US20120126292A1

公开(公告)日：2012-05-24

申请号：US12951516

申请日：2010-11-22

申请人： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

发明人： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

IPC分类号： H01L29/737 ,  G06F9/45 ,  H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

摘要翻译： 具有降低的基极电阻的异质结双极晶体管，以及用于BiCMOS集成电路的异质结双极晶体管和设计结构的制造方法。 异质结双极晶体管包括在本征基极和外部基极之间的导电层。 导电层由诸如硅化物的导电材料构成，其电阻率低于形成本征碱和非本征基的材料。