公开(公告)号：US20230376415A1

公开(公告)日：2023-11-23

申请号：US18186476

申请日：2023-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Yonghua WANG

IPC: G06F12/08 ,  G06F7/523 ,  G06F7/50

CPC classification number: G06F12/08 ,  G06F7/523 ,  G06F7/50 ,  G06F2213/28

Abstract: A semiconductor device capable of reducing power consumption is provided. A group controller detects a zero weight parameter having a zero value among “n×m” weight parameters to be transferred to a weight parameter buffer. Then, when receiving the zero weight parameter as its input, the group controller exchanges the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero. The group controller controls the target multiplier group to be disabled, and exchanges the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.

公开(公告)号：US20220398441A1

公开(公告)日：2022-12-15

申请号：US17345368

申请日：2021-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

IPC: G06N3/063 ,  G06F13/20 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: A semiconductor device executes the processing of a neural network. The memory MEM1 holds a plurality of pixel values and j compressed weighting factors. The decompressor DCMP restores the j compressed weighting factors to the uncompressed k (k≥j) weighting factors. The DMA controller DMAC1 reads the j compressed weighting factors from the memory MEM1 and transfers them to the decompressor DCMP. The n (n>k) accumulators in the accumulator unit ACCU multiply a plurality of pixel values and k uncompressed weighting factor to accumulate and add the multiplication results to the time series. A switch circuit SW1 provided between the decompressor DCMP and the accumulator unit ACCU transfers the k uncompressed weighting factors restored by the decompressor DCMP to n accumulators based on the correspondence represented by the identifier.

公开(公告)号：US20190039607A1

公开(公告)日：2019-02-07

申请号：US16031789

申请日：2018-07-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Yuki KAJIWARA

IPC: B60W30/09 ,  G05D1/02 ,  G05D1/00 ,  B60Q5/00

Abstract: A mobile object control system has an SfM unit detecting distance to an object imaged by a monocular camera by using the SfM algorithm, a first-stop-position output unit outputting a first stop position, a second-stop-position calculating unit calculating a second stop position closer than the first stop position, and a control unit controlling travel of a mobile object. The control unit controls the mobile object so as to stop at the second stop position. When a predetermined starting condition is satisfied, the control unit controls the mobile object so as to start. The SfM unit detects the distance to an object by using an image captured by the monocular camera after the mobile object starts. When a result of detection of the distance of the object by the SfM unit is obtained, the control unit uses the detection result for control of the travel.

公开(公告)号：US20240104034A1

公开(公告)日：2024-03-28

申请号：US18348534

申请日：2023-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Rajesh GHIMIRE

IPC: G06F13/28 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F13/28 ,  G06T1/20 ,  G06T1/60

Abstract: A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.

公开(公告)号：US20230162315A1

公开(公告)日：2023-05-25

申请号：US17531302

申请日：2021-11-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

IPC: G06T1/20 ,  G06T7/11 ,  G06T3/40 ,  G06T1/00

CPC classification number: G06T1/20 ,  G06T7/11 ,  G06T3/4015 ,  G06T1/0007

Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

公开(公告)号：US20230162013A1

公开(公告)日：2023-05-25

申请号：US17954831

申请日：2022-09-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Manabu KOIKE

IPC: G06N3/063 ,  G06F5/01 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/5443

Abstract: A semiconductor device according to one embodiment executes a neural network processing. A first shift register sequentially generates a plurality of pieces of quantized input data by quantizing a plurality of pieces of output data sequentially inputted from a first buffer by bit-shifting. A product-sum operator generates operation data by performing a product-sum operation to a plurality of parameters and the plurality of pieces of quantized input data from the first shift register. The second shift register generates the output data by inversely quantizing the operation data from the product-sum operator by bit-shifting, and stores the output data in the first buffer.

公开(公告)号：US20210349819A1

公开(公告)日：2021-11-11

申请号：US16868041

申请日：2020-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NAKAMURA ,  Akihiro YAMAMOTO ,  Kazuaki TERASHIMA ,  Manabu KOIKE

IPC: G06F12/06 ,  G06F12/02 ,  G06F9/48 ,  G06F9/30 ,  G06F9/52 ,  G06F13/16 ,  G11C11/408

Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.