公开(公告)号：US06912173B2

公开(公告)日：2005-06-28

申请号：US10178270

申请日：2002-06-25

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C7/10 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C7/1006

Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

Abstract translation: 地址设备使用第一地址总线和使用第二地址总线的第二存储器部分的第二增量更高的地址同时向第一存储器部分提供第一地址。 然后可以从第一和第二存储器部分读取或写入缓冲器。 在读取操作期间，缓冲器可以从第一存储器部分接收未对齐数据字的第一部分，并且从第二存储器部分读取未对齐数据字的第二部分，并且将数据字中的数据从第一和第二 部分。 当访问操作是写入操作时，缓冲器可以有效地对数据字中的数据执行移位操作，然后将字的第一部分写入第一存储器部分，并将该字的第二部分写入第二存储器 部分。 因此，在常规存储器系统上将需要两个存储器访问周期的数据访问被减少到单个存储器访问周期。

公开(公告)号：US06864721B2

公开(公告)日：2005-03-08

申请号：US10232255

申请日：2002-08-29

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C8/10 ,  G11C11/418 ,  G11C8/00

CPC classification number: G11C11/418 ,  G11C8/10

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

Abstract translation: 一种解码电路，用于根据多条输入线的状态选择多条输出线之一，该电路包括：第一解码装置，包括：第一解码节点; 第一预充电电路，用于将第一解码节点充电到充电电位; 第一放电电路包括多个开关装置，每个开关装置可根据输入线的相应一个的状态进行操作，以将第一解码节点耦合到放电电位; 以及第一选择电路，其耦合到所述输出线中的相应一个，并且响应于第一使能信号可操作以在所述第一解码节点尚未放电时选择所述输出线; 以及第二解码装置，包括：第二解码节点; 第二预充电电路，用于将第二解码节点充电到充电电位; 第二放电电路包括多个开关装置，每个切换装置可根据输入线的相应一个的状态进行操作，以将第二解码节点耦合到放电电位; 以及第二选择电路，其耦合到所述输出线中的相应一个，并且响应于第二使能信号可操作以在所述第二放电节点尚未放电时选择所述输出线; 其中所述第一使能信号从所述第二解码节点的电位导出。

公开(公告)号：US06789179B2

公开(公告)日：2004-09-07

申请号：US10178269

申请日：2002-06-25

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G06F1206

CPC classification number: G11C7/22 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/108

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Abstract translation: 第一和第二地址选择信息以及第一和第二读/写信息同时提供给各种使能电路。 然后，使能电路可以基于第一地址选择和第一读/写信息来启用一个或多个第一存储器单元，并且还基于第二地址选择信息和读/写信息使一个或多个第二存储器单元启用。 然后可以在单个存储器访问周期中将数据写入或读取启用的存储器单元。

公开(公告)号：US06614701B2

公开(公告)日：2003-09-02

申请号：US10119636

申请日：2002-04-10

Applicant: William Bryan Barnes ,  Robert Beat

Inventor： William Bryan Barnes ,  Robert Beat

IPC: G11C700

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C29/50

Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching device, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching device, activatable by the common word line, for coupling the second node to a respective second bit-line; and a respective individual gate arrangement having an output, and inputs connected to the respective first and second bit-lines; and the apparatus comprising a common gate arrangement having an output, and inputs connected to the outputs of the individual gate arrangements.

Abstract translation: 用于测试集成电路的装置，所述集成电路包括由公共字线连接的多个半导体存储器单元，每个存储单元包括：交叉耦合布置的相应的第一和第二晶体管，以形成双稳态锁存器， 第一晶体管表示用于存储高电位或低电位状态的相应第一节点，并且连接到相应的第一半导体装置，用于替换从第一节点泄漏的电荷并连接到由公共字线激活的相应的第一开关装置， 用于将相应的第一节点耦合到相应的第一位线，所述第二晶体管的漏极表示用于存储高或低电位状态的相应的第二节点，并且连接到相应的第二半导体装置，用于替换从相应的第二位线泄漏的电荷 节点并且连接到相应的第二开关装置，由c可激活 ommon字线，用于将第二节点耦合到相应的第二位线; 以及具有输出的各自的单独门装置和连接到相应的第一和第二位线的输入; 并且所述装置包括具有输出的公共门装置，以及连接到各个门装置的输出的输入。

公开(公告)号：US06456118B2

公开(公告)日：2002-09-24

申请号：US09759832

申请日：2001-01-12

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C800

CPC classification number: G11C11/418 ,  G11C8/10

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

Abstract translation: 一种解码电路，用于根据多条输入线的状态选择多条输出线之一，该电路包括：第一解码装置，包括：第一解码节点; 第一预充电电路，用于将第一解码节点充电到充电电位; 第一放电电路包括多个开关装置，每个开关装置可根据输入线的相应一个的状态进行操作，以将第一解码节点耦合到放电电位;以及第一选择电路，耦合到相应的一个输出线，并可操作 响应于第一使能信号，如果第一解码节点尚未放电则选择该输出线; 以及第二解码装置，包括：第二解码节点; 第二预充电电路，用于将第二解码节点充电到充电电位; 第二放电电路包括多个开关装置，每个切换装置可根据输入线的相应一个的状态进行操作，以将第二解码节点耦合到放电电位; 以及第二选择电路，其耦合到所述输出线中的相应一个，并且响应于第二使能信号可操作以在所述第二放电节点尚未放电时选择所述输出线; 其中所述第一使能信号从所述第二解码节点的电位导出。