公开(公告)号：US5687352A

公开(公告)日：1997-11-11

申请号：US519169

申请日：1995-08-25

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C17/00 ,  G11C7/00 ,  G11C8/00 ,  G11C16/02 ,  G11C16/06 ,  G06F13/00

CPC classification number: G11C8/00 ,  G11C16/06 ,  G11C7/00

Abstract: A memory device has a data storage portion and at least peripheral circuit connected to the data storage portion for carrying out a function with respect to the data storage portion. The memory device also has control circuitry connected to the at least one peripheral circuit and operable to provide a plurality of consecutive signals for controlling the function of said at least one peripheral circuit. The consecutive signals generated by the control circuitry are in the form of Gray code.

Abstract translation: 存储器装置具有数据存储部分，并且至少外围电路连接到数据存储部分，用于执行关于数据存储部分的功能。 存储器件还具有连接到至少一个外围电路的控制电路，并且可操作以提供用于控制所述至少一个外围电路的功能的多个连续信号。 由控制电路产生的连续信号是格雷码的形式。

公开(公告)号：US07049851B2

公开(公告)日：2006-05-23

申请号：US11067652

申请日：2005-02-28

Applicant: Robert Beat

Inventor： Robert Beat

IPC: H03K19/094

CPC classification number: G11C11/418 ,  G11C8/10

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

公开(公告)号：US20070055832A1

公开(公告)日：2007-03-08

申请号：US11598010

申请日：2006-11-13

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G06F13/00

CPC classification number: G11C7/22 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/108

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

公开(公告)号：US20050180240A1

公开(公告)日：2005-08-18

申请号：US11102641

申请日：2005-04-11

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1006

Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

公开(公告)号：US5959465A

公开(公告)日：1999-09-28

申请号：US581737

申请日：1995-12-29

Applicant: Robert Beat

Inventor： Robert Beat

IPC: H03K19/177

CPC classification number: H03K19/1772

Abstract: A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.

Abstract translation: 提供了一种用于在集成电路中操作可编程逻辑阵列的方法。 电路的每一级仅在该级传播输入信号所需的时间内被使能。 使用在电路的尺寸，方向和连接性上复制电路元件的虚拟电路产生电路级的使能信号。 这些元件提供延迟路径，使得与可编程逻辑阵列电路同时施加的输入信号和虚拟电路产生虚拟电路的输出，该输出定义用于从可编程逻辑阵列电路的级施加和去除使能信号的时间。

公开(公告)号：US07302545B2

公开(公告)日：2007-11-27

申请号：US11598010

申请日：2006-11-13

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G06F12/06

CPC classification number: G11C7/22 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/108

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Abstract translation: 第一和第二地址选择信息以及第一和第二读/写信息同时提供给各种使能电路。 然后，使能电路可以基于第一地址选择和第一读/写信息来启用一个或多个第一存储器单元，并且还基于第二地址选择信息和读/写信息使一个或多个第二存储器单元启用。 然后可以在单个存储器访问周期中将数据写入或读取启用的存储器单元。

公开(公告)号：US20050141329A1

公开(公告)日：2005-06-30

申请号：US11067652

申请日：2005-02-28

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C8/10 ,  G11C11/418 ,  G11C8/00

CPC classification number: G11C11/418 ,  G11C8/10

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

Abstract translation: 一种解码电路，用于根据多条输入线的状态选择多条输出线之一，该电路包括：第一解码装置，包括：第一解码节点; 第一预充电电路，用于将第一解码节点充电到充电电位; 第一放电电路包括多个开关装置，每个开关装置可根据输入线的相应一个的状态进行操作，以将第一解码节点耦合到放电电位;以及第一选择电路，耦合到相应的一个输出线，并可操作 响应于第一使能信号，如果第一解码节点尚未放电则选择该输出线; 以及第二解码装置，包括：第二解码节点; 第二预充电电路，用于将第二解码节点充电到充电电位; 第二放电电路包括多个开关装置，每个切换装置可根据输入线的相应一个的状态进行操作，以将第二解码节点耦合到放电电位; 以及第二选择电路，其耦合到所述输出线中的相应一个，并且响应于第二使能信号可操作以在所述第二放电节点尚未放电时选择所述输出线; 其中所述第一使能信号从所述第二解码节点的电位导出。

公开(公告)号：US6052806A

公开(公告)日：2000-04-18

申请号：US519192

申请日：1995-08-25

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G01R31/28 ,  G06F11/27 ,  G11C17/00 ,  G11C29/00 ,  G11C29/12

CPC classification number: G06F11/27

Abstract: An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for carrying out at least one function in respect of the operational circuitry. Input means are provided to permit the input of command data in a normal mode of operation and to permit the input of test data in a test mode of operation. Control circuitry has an input to receive command data from the input means. The control circuitry is arranged to generate, in response to the command data, control signals to control at least one of the peripheral circuits in the normal mode of operation. A control bus is connected between the control circuitry and the peripheral circuits and is arranged to carry control signals from the control circuitry to at least one peripheral circuit. Test circuitry is also provided which has an input arranged to receive test data from the input means. The test circuitry also has an output connected to the control bus and is arranged such that in the test mode of operation, the test data is supplied to at least one peripheral circuit from the test circuitry via the control bus.

Abstract translation: 集成电路装置包括例如用于执行集成电路装置的操作的存储器形式的操作电路。 此外，至少一个外围电路连接到操作电路，用于执行关于操作电路的至少一个功能。 提供输入装置以允许在正常操作模式下输入命令数据，并允许在测试操作模式下输入测试数据。 控制电路具有从输入装置接收命令数据的输入。 控制电路被布置成响应于命令数据产生控制信号，以控制正常操作模式中的至少一个外围电路。 控制总线连接在控制电路和外围电路之间，并被布置成将控制信号从控制电路传送到至少一个外围电路。 还提供测试电路，其具有布置成从输入装置接收测试数据的输入。 测试电路还具有连接到控制总线的输出，并且被布置为使得在测试操作模式下，测试数据经由控制总线从测试电路提供给至少一个外围电路。

公开(公告)号：US5606584A

公开(公告)日：1997-02-25

申请号：US519314

申请日：1995-08-25

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/06 ,  H03K5/15 ,  H03K23/54 ,  H03K23/66 ,  G06M3/00

CPC classification number: H03K5/15093 ,  H03K23/54 ,  H03K23/665

Abstract: The current invention provides a timer circuit for timing a plurality of time periods. The timer circuit has a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values.A first timing signal generator generates a first timing signal to indicate the expiry of a first time period by detecting the first occurrence of the second logic value (0), in a subset of the set of logic states at the set of state outputs. A second timing signal generator generates a second timing signal to indicate the expiry of a second time period by detecting a predetermined combination of logic values at the set of state outputs.

Abstract translation: 本发明提供了一种用于定时多个时间段的定时器电路。 定时器电路具有用于接收定时脉冲的定时脉冲输入; 一组状态输出处于一组逻辑状态，每个逻辑状态采用两个逻辑值中的一个，逻辑状态集合的逻辑值在每个定时脉冲处改变; 多个定时输出，每个定时输出在预定时间段到期时提供信号; 以及用于复位定时电路并且用于定义初始逻辑状态集合的复位信号。 逻辑状态集合遵循逻辑值集合的第一序列，从逻辑值的初始集合开始，其中除了至少一个逻辑状态之外，每个集合内的所有逻辑状态都处于第一逻辑值（1），其中 处于第二逻辑值（0），在第一逻辑值集合中的逻辑值集合中的每一组中承载异常状态的不同状态输出。 第一定时信号发生器通过在状态输出集合的逻辑状态集合的子集中检测第二逻辑值（0）的第一次出现来产生第一定时信号以指示第一时间段的到期。 第二定时信号发生器通过检测状态输出集合上的逻辑值的预定组合来产生第二定时信号以指示第二时间段的期满。

公开(公告)号：US07136985B2

公开(公告)日：2006-11-14

申请号：US10894027

申请日：2004-07-20

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G06F12/06

CPC classification number: G11C7/22 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/108

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.