公开(公告)号：US20100081245A1

公开(公告)日：2010-04-01

申请号：US12240682

申请日：2008-09-29

Applicant: Frank Bin YANG ,  Rohit PAL ,  Michael J. HARGROVE

Inventor： Frank Bin YANG ,  Rohit PAL ,  Michael J. HARGROVE

IPC: H01L21/336

CPC classification number: H01L29/7847 ,  H01L29/66636

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract translation: 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，沉积覆盖栅电极的应力诱导层，退火含硅衬底以重结晶 栅电极，去除应力诱导层，使用栅电极作为蚀刻掩模蚀刻到衬底中的凹槽，以及在凹槽中外延生长杂质掺杂的含硅区域。

公开(公告)号：US20100059852A1

公开(公告)日：2010-03-11

申请号：US12209056

申请日：2008-09-11

Applicant: Rohit PAL ,  David BROWN ,  Scott LUNING

Inventor： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device structure is provided. The method begins by providing a substrate having a layer of semiconductor material, a pad oxide layer overlying the layer of semiconductor material, and a pad nitride layer overlying the pad oxide layer. The method proceeds by selectively removing a portion of the pad nitride layer, a portion of the pad oxide layer, and a portion of the layer of semiconductor material to form an isolation trench. Then, the isolation trench is filled with a lower layer of isolation material, a layer of etch stop material, and an upper layer of isolation material, such that the layer of etch stop material is located between the lower layer of isolation material and the upper layer of isolation material. The layer of etch stop material protects the underlying isolation material during subsequent fabrication steps.

Abstract translation: 提供一种制造半导体器件结构的方法。 该方法开始于提供具有半导体材料层的衬底，覆盖在半导体材料层上的衬垫氧化物层和覆盖衬垫氧化物层的衬垫氮化物层。 该方法通过选择性地去除衬垫氮化物层的一部分，衬垫氧化物层的一部分和半导体材料层的一部分来形成隔离沟槽。 然后，隔离沟槽填充有较低层的隔离材料，一层蚀刻停止材料和上层隔离材料，使得该蚀刻停止材料层位于隔离材料的下层和上部隔离层之间 隔离材料层。 蚀刻停止材料层在随后的制造步骤期间保护下面的隔离材料。

公开(公告)号：US20090256201A1

公开(公告)日：2009-10-15

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

Inventor： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US20110204446A1

公开(公告)日：2011-08-25

申请号：US13098065

申请日：2011-04-29

Applicant: Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

Inventor： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC: H01L29/78

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US20110169084A1

公开(公告)日：2011-07-14

申请号：US12687610

申请日：2010-01-14

Applicant: Bin YANG ,  Rohit PAL ,  Michael HARGROVE

Inventor： Bin YANG ,  Rohit PAL ,  Michael HARGROVE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/86

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US20110121397A1

公开(公告)日：2011-05-26

申请号：US13021403

申请日：2011-02-04

Applicant: Rohit PAL ,  Michael HARGROVE ,  Frank Bin YANG

Inventor： Rohit PAL ,  Michael HARGROVE ,  Frank Bin YANG

IPC: H01L29/78

CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

公开(公告)号：US20100109056A1

公开(公告)日：2010-05-06

申请号：US12330292

申请日：2008-12-08

Applicant: Rohit PAL ,  Man Fai NG ,  David BROWN

Inventor： Rohit PAL ,  Man Fai NG ,  David BROWN

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

公开(公告)号：US20090176356A1

公开(公告)日：2009-07-09

申请号：US11971481

申请日：2008-01-09

Applicant: Rohit PAL ,  Jon KLUTH ,  David BROWN

Inventor： Rohit PAL ,  Jon KLUTH ,  David BROWN

IPC: H01L21/22

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/7848

Abstract: Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces a predetermined thermal gradient between the first region and the second region.

Abstract translation: 提供了使用热梯度诱导膜制造半导体器件的方法。 一种方法包括提供具有第一区域和第二区域的衬底，并形成覆盖第二区域并暴露第一区域的膜。 对衬底进行热处理，其中膜在第一区域和第二区域之间引起预定的热梯度。

公开(公告)号：US20080220579A1

公开(公告)日：2008-09-11

申请号：US11683174

申请日：2007-03-07

Applicant: Rohit PAL ,  David BROWN ,  Scott LUNING

Inventor： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC: H01L21/336 ,  H01L29/94

CPC classification number: H01L29/0847 ,  H01L21/31662 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

Abstract: According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The first and second side surfaces are formed astride the channel region. The first and second side surfaces are then oxidized in a controlled oxidizing environment to thereby grow an oxide region. The oxide region is then removed, thereby repositioning the first and second side surfaces closer to the channel region. With the first and second side surfaces repositioned, the first and second trenches are filled with SiGe.

Abstract translation: 根据用于制造在半导体衬底的表面具有沟道区的应力增强型MOS器件的方法，第一和第二沟槽被蚀刻到半导体衬底中，第一沟槽具有第一侧表面，并且第二沟槽具有第二沟槽 侧面。 第一和第二侧表面跨越通道区域形成。 然后将第一和第二侧表面在受控的氧化环境中氧化，从而生长氧化物区域。 然后去除氧化物区域，从而将第一和第二侧表面重新定位成更靠近沟道区域。 在第一和第二侧表面重新定位时，第一和第二沟槽被填充有SiGe。