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公开(公告)号：US20240429943A1
公开(公告)日：2024-12-26
申请号：US18584838
申请日：2024-02-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kijun Jeon , Kyoungbin Park , Minki Song , Dongmin Shin , Daeyeol Yang , Bohwan Jun , Youngjun Hwang
Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.
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公开(公告)号：US20240356565A1
公开(公告)日：2024-10-24
申请号：US18643302
申请日：2024-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Bohwan Jun , Youngjun Hwang , Dongmin Shin
CPC classification number: H03M13/1174 , H03M13/1575 , H03M13/3746
Abstract: An example operating method of an error correction code (ECC) circuit includes receiving a codeword from a memory device, calculating a syndrome vector based on the codeword and a parity-check matrix indicating whether messages are exchanged between check nodes and variable nodes, performing, when the syndrome vector is not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by decoding a first column in a first operation mode, the first column having a first variable node degree, decoding a second column in a second operation mode, the second column having a second variable node degree, and decoding a third column in a third operation mode, the third column having a third variable node degree, and calculating the syndrome vector whenever the sequential decoding of the plurality of columns is completed and iteratively performing the sequential decoding until the syndrome vector is the zero vector.
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公开(公告)号：US10789127B2
公开(公告)日：2020-09-29
申请号：US16057855
申请日：2018-08-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Geunyeong Yu , Bohwan Jun , Kijun Lee , Junjin Kong , Hong-Rak Son
Abstract: A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.
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Patent Agency Ranking
公开(公告)号：US12273127B2
公开(公告)日：2025-04-08
申请号：US18218294
申请日：2023-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehun Jang , Mankeun Seo , Hongrak Son , Bohwan Jun
Abstract: An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.
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公开(公告)号：US20240184669A1
公开(公告)日：2024-06-06
申请号：US18218294
申请日：2023-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehun Jang , Mankeun Seo , Hongrak Son , Bohwan Jun
IPC: G06F11/10
CPC classification number: G06F11/1044 , G06F11/1012
Abstract: An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.
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公开(公告)号：US11664826B2
公开(公告)日：2023-05-30
申请号：US17478002
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Geunyeong Yu , Heeyoul Kwak , Hongrak Son , Dongmin Shin , Wijik Lee , Bohwan Jun , Youngjun Hwang
CPC classification number: H03M13/2948 , H03M13/096 , H03M13/1108 , H03M13/1575
Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.
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公开(公告)号：US20230163785A1
公开(公告)日：2023-05-25
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1134 , H03M13/112
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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公开(公告)号：US11562803B2
公开(公告)日：2023-01-24
申请号：US17244195
申请日：2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Heeyoul Kwak , Bohwan Jun , Hongrak Son , Dongmin Shin , Geunyeong Yu
Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.
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