公开(公告)号：US11917822B2

公开(公告)日：2024-02-27

申请号：US17036997

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

公开(公告)号：US11839091B2

公开(公告)日：2023-12-05

申请号：US17011156

申请日：2020-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Bonghyun Choi ,  Siwan Kim

IPC: H10B43/20 ,  H10B69/00

CPC classification number: H10B69/00 ,  H10B43/20

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.