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公开(公告)号：US11616021B2
公开(公告)日：2023-03-28
申请号：US17021321
申请日：2020-09-15
发明人： Seungjun Shin , Siwan Kim , Bonghyun Choi
IPC分类号： H01L23/528 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11573 , H01L23/522 , H01L27/11582
摘要： A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.
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公开(公告)号：US20210242236A1
公开(公告)日：2021-08-05
申请号：US17036997
申请日：2020-09-29
发明人： Seungjun Shin , Siwan Kim , Bonghyun Choi
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11519 , H01L27/11556 , H01L23/522
摘要： A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.
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公开(公告)号：US20240040792A1
公开(公告)日：2024-02-01
申请号：US18356324
申请日：2023-07-21
发明人： Youngshik Yun , Dongsik Lee , Siwan Kim , Sori Lee , Bongtae Park , Jaejoo Shim
IPC分类号： H10B43/40 , H10B43/27 , H10B43/35 , H10B41/40 , H10B41/27 , H10B41/35 , G11C16/04 , H01L23/528 , H10B80/00 , H01L25/065
CPC分类号： H10B43/40 , H10B43/27 , H10B43/35 , H10B41/40 , H10B41/27 , H10B41/35 , G11C16/0483 , H01L23/5283 , H10B80/00 , H01L25/0652 , H01L2225/06541
摘要： A semiconductor device includes a peripheral circuit region and a memory cell region. The memory cell region may include a stack structure including gate electrodes and interlayer insulating layers repeatedly and alternately stacked in a vertical direction, and a channel structure penetrating through the stack structure. The gate electrodes may include first gate electrodes, second gate electrodes on the first gate electrodes, and third gate electrodes on the second gate electrodes. Each of the first gate electrodes may have a first thickness. Each of the second gate electrodes may have a second thickness that is greater than the first thickness. Each of the third gate electrodes may have a third thickness that is smaller than the second thickness.
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公开(公告)号：US11810776B2
公开(公告)日：2023-11-07
申请号：US17021321
申请日：2020-09-15
发明人： Seungjun Shin , Siwan Kim , Bonghyun Choi
IPC分类号： H01L23/528 , H01L23/535 , H01L23/522 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
CPC分类号： H01L23/535 , H01L23/5226 , H01L23/5283 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
摘要： A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.
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公开(公告)号：US11211029B2
公开(公告)日：2021-12-28
申请号：US17023752
申请日：2020-09-17
发明人： Dongyeong Cheon , Minkyu Park , Daewon Kim , Siwan Kim , Ukhyun Kim , Junho Lee , Eunsil Lim , Jungwoo Choi
IPC分类号： G09G5/00 , G09G5/02 , G06T7/90 , G09G5/37 , G06F3/0482
摘要： An electronic device and method are disclosed herein. The electronic device includes a display, and a processor. The processor implements the method, including: acquiring a background image of a screen generated for display, a region of interest (ROI) where a user interface (UI) element is to be displayed, calculating a value indicating a shape complexity of the ROI, dividing the ROI into a plurality of clusters according to designated attributes, calculating difference values indicating a contrast between each of the plurality of clusters and the UI element, identifying a minimum difference value from among the difference values as a contrast difference value, calculating a result value indicating a degree of visibility of the UI element relative to the background image, determining an image effect to be applied to the UI element, based on the result value, and display to the altered ROI the UI element.
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公开(公告)号：US11917822B2
公开(公告)日：2024-02-27
申请号：US17036997
申请日：2020-09-29
发明人： Seungjun Shin , Siwan Kim , Bonghyun Choi
IPC分类号： H10B43/27 , H01L23/522 , H10B41/10 , H10B41/27 , H10B43/10
CPC分类号： H10B43/27 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B43/10
摘要： A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.
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公开(公告)号：US11839091B2
公开(公告)日：2023-12-05
申请号：US17011156
申请日：2020-09-03
发明人： Junhyoung Kim , Kwang-Soo Kim , Bonghyun Choi , Siwan Kim
摘要： A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.
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