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    Vertical memory devices and methods of manufacturing the same
    1.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权

    公开(公告)号：US12207469B2

    公开(公告)日：2025-01-21

    申请号：US18386112

    申请日：2023-11-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung Kim ,  Seonho Yoon ,  Bonghyun Choi

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

    Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11856773B2

    公开(公告)日：2023-12-26

    申请号：US17176398

    申请日：2021-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

    IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

    Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210242236A1

    公开(公告)日：2021-08-05

    申请号：US17036997

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/522

    Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

    Vertical memory devices
    5.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11818889B2

    公开(公告)日：2023-11-14

    申请号：US17567364

    申请日：2022-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung Kim ,  Seonho Yoon ,  Bonghyun Choi

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

    Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

    Vertical memory devices and methods of manufacturing the same
    7.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权

    公开(公告)号：US11217603B2

    公开(公告)日：2022-01-04

    申请号：US16850097

    申请日：2020-04-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung Kim ,  Seonho Yoon ,  Bonghyun Choi

    IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

    Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

    Semiconductor device including stack structure with flat region
    8.
    发明授权
    Semiconductor device including stack structure with flat region 有权

    公开(公告)号：US11616021B2

    公开(公告)日：2023-03-28

    申请号：US17021321

    申请日：2020-09-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11582

    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210375920A1

    公开(公告)日：2021-12-02

    申请号：US17176398

    申请日：2021-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519

    Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

    Semiconductor device with stacked structure
    10.
    发明授权
    Semiconductor device with stacked structure 有权

    公开(公告)号：US12283548B2

    公开(公告)日：2025-04-22

    申请号：US18125177

    申请日：2023-03-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

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