公开(公告)号：US20210357287A1

公开(公告)日：2021-11-18

申请号：US17132028

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoun KIM ,  Kijun LEE ,  Chanki KIM ,  Myungkyu LEE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15

Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.

公开(公告)号：US20210311820A1

公开(公告)日：2021-10-07

申请号：US17351619

申请日：2021-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn CHA ,  Hoyoung SONG ,  Myungkyu LEE ,  Sunghye CHO

IPC: G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US20210193245A1

公开(公告)日：2021-06-24

申请号：US16864787

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn CHA ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Youngcheon KWON ,  Jaeyoun YOUN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.