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公开(公告)号：US09727474B2
公开(公告)日：2017-08-08
申请号：US13966889
申请日：2013-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD. , INDUSTRY & ACADEMIC COOPERATION GROUP OF SEJONG UNIVERSITY
Inventor： Kwon Taek Kwon , Youngsik Kim , Woo Chan Park , Young Duke Seo , Sang Oak Woo , Seok Yoon Jung , Duk Ki Hong
IPC: G09G5/36 , G06F12/0875 , G06F12/0855
CPC classification number: G06F12/0875 , G06F12/0855
Abstract: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.
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Patent Agency Ranking
12.发明授权Apparatus and method for non-blocking execution of static scheduled processor 有权用于非阻塞执行静态预定处理器的装置和方法公开(公告)号：US09405546B2
公开(公告)日：2016-08-02
申请号：US14199154
申请日：2014-03-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwon Taek Kwon , Sang Oak Woo , Shi Hwa Lee , Seok Yoon Jung
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/3832 , G06F9/3842 , G06F9/3859
Abstract: An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.
Abstract translation: 一种用于非阻塞执行静态预定处理器的装置和方法，该装置包括处理器，用于使用传送的输入数据处理至少一个操作，以及用于将输入数据传送到处理器的输入缓冲器， 处理所述至少一个操作，其中所述处理器可以包括执行所述至少一个操作的至少一个功能单元（FU），并且所述至少一个FU可以使用常规等待时间操作和 不规则的延迟操作。
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公开(公告)号：US09256536B2
公开(公告)日：2016-02-09
申请号：US13873972
申请日：2013-04-30
Inventor： Jeong Ae Park , Sang Oak Woo , Seok Yoon Jung , Young sik Kim , Woo Chan Park
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0875 , G06F2212/455 , G06F2212/601
Abstract: A method and apparatus for providing shared caches. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, at least one bit may overlap tag bits and set index bits among bits of a memory address.
Abstract translation: 一种用于提供共享缓存的方法和装置。 高速缓冲存储器系统可以以第一模式或第二模式操作。 当高速缓冲存储器系统在第一模式下操作时，可以独立地操作高速缓冲存储器系统的第一高速缓存和第二高速缓存。 当高速缓冲存储器系统在第二模式下操作时，可以共享第一高速缓存和第二高速缓存。 在第二模式中，至少一个位可以与存储器地址的位之间的标签位重叠并设置索引位。
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14.发明授权公开(公告)号：US09176880B2
公开(公告)日：2015-11-03
申请号：US13652894
申请日：2012-10-16
Inventor： Won Jong Lee , Sang Oak Woo , Seok Yoon Jung , Woo Chan Park , Young Sik Kim
CPC classification number: G06F12/0864 , G06F12/126 , G06T1/60 , Y02D10/13
Abstract: A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.
Abstract translation: 可以提供用于基于瓦片的呈现的高速缓冲存储器系统和缓存方法。 缓存存储器系统中的每个高速缓存行可以包括延迟替换信息。 延迟替换信息可以指示在高速缓存行中是否包括在瓦片的边缘的位置处引用的纹理数据。 当高速缓冲存储器系统中不存在对应于访问请求地址的高速缓存行时，高速缓冲存储器系统可以基于延迟替换信息来从关联高速缓存单元中选择和移除要移除的高速缓存行。
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公开(公告)号：US20140152650A1
公开(公告)日：2014-06-05
申请号：US13875585
申请日：2013-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung Jin Son , Sang Oak Woo , Seok Yoon Jung
IPC: G06T15/00
CPC classification number: G06T1/60 , G06T15/005
Abstract: A method for tile-based rendering may include verifying a size of a memory available in an apparatus for rendering, and determining a number of buffers required for performing a rendering based on graphics data input, and may further include determining a size of a tile to be used for performing the rendering based on the determined number of buffers and the size of the memory available.
Abstract translation: 用于基于瓦片的呈现的方法可以包括验证用于呈现的设备中可用的存储器的大小，以及基于图形数据输入来确定执行渲染所需的缓冲器的数量，并且还可以包括确定块的大小 用于基于确定的缓冲器数量和可用存储器的大小执行渲染。
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公开(公告)号：US20130346696A1
公开(公告)日：2013-12-26
申请号：US13873972
申请日：2013-04-30
Inventor： Jeong Ae Park , Sang Oak Woo , Seok Yoon Jung , Young sik Kim , Woo Chan Park
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0875 , G06F2212/455 , G06F2212/601
Abstract: A method and apparatus for providing shared caches. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, at least one bit may overlap tag bits and set index bits among bits of a memory address.
Abstract translation: 一种用于提供共享缓存的方法和装置。 高速缓冲存储器系统可以以第一模式或第二模式操作。 当高速缓冲存储器系统在第一模式下操作时，可以独立地操作高速缓冲存储器系统的第一高速缓存和第二高速缓存。 当高速缓冲存储器系统在第二模式下操作时，可以共享第一高速缓存和第二高速缓存。 在第二模式中，至少一个位可以与存储器地址的位之间的标签位重叠并设置索引位。
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