公开(公告)号：USD730907S1

公开(公告)日：2015-06-02

申请号：US29507079

申请日：2014-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Gwang-Man Lim ,  Il-Mok Kang ,  Seok-Jae Han ,  Sang-Chul Kang ,  Seok-Cheon Kwon ,  Seok-Chan Lee

公开(公告)号：US09715936B2

公开(公告)日：2017-07-25

申请号：US15062546

申请日：2016-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeong-Han Lee ,  Seok-Cheon Kwon ,  Dong-Yang Lee

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C7/22 ,  G11C7/10 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

公开(公告)号：US09281072B2

公开(公告)日：2016-03-08

申请号：US14856261

申请日：2015-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeong-Han Lee ,  Seok-Cheon Kwon ,  Dong-Yang Lee

IPC: G11C16/32 ,  G11C7/22 ,  G11C16/26 ,  G11C16/08 ,  G11C7/10

CPC classification number: G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract translation: 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出​​第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。

公开(公告)号：US20160005483A1

公开(公告)日：2016-01-07

申请号：US14856218

申请日：2015-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYEONG-HAN LEE ,  Seok-Cheon Kwon ,  Dong-Yang Lee

IPC: G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

公开(公告)号：USD735725S1

公开(公告)日：2015-08-04

申请号：US29507436

申请日：2014-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Gwang-Man Lim ,  Il-Mok Kang ,  Seok-Jae Han ,  Sang-Chul Kang ,  Seok-Cheon Kwon ,  Seok-Chan Lee