公开(公告)号：US20210055985A1

公开(公告)日：2021-02-25

申请号：US16882601

申请日：2020-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Youngjin CHO ,  Seungwon LEE

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/25

Abstract: A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.

公开(公告)号：US20200065659A1

公开(公告)日：2020-02-27

申请号：US16550498

申请日：2019-08-26

Applicant: Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

Inventor： Seungwon LEE ,  Hanmin PARK ,  Gunhee LEE ,  Namhyung KIM ,  Joonsang YU ,  Kiyoung CHOI

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A method of accelerating a training process of a neural network includes acquiring activations used in the training process and a bit-vector corresponding to the activations, selecting activations requiring an operation from among the acquired activations by using the bit-vector, and performing backward propagation using the selected activations and filters corresponding to the selected activations.

公开(公告)号：US20190122100A1

公开(公告)日：2019-04-25

申请号：US16160444

申请日：2018-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Seungwon LEE

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/499 ,  G06F7/57

Abstract: Provided is a processor implemented method that includes performing training or an inference operation with a neural network by obtaining a parameter for the neural network in a floating-point format, applying a fractional length of a fixed-point format to the parameter in the floating-point format, performing an operation with an integer arithmetic logic unit (ALU) to determine whether to round off a fixed point based on a most significant bit among bit values to be discarded after a quantization process, and performing an operation of quantizing the parameter in the floating-point format to a parameter in the fixed-point format, based on a result of the operation with the ALU.

公开(公告)号：US20240256277A1

公开(公告)日：2024-08-01

申请号：US18456874

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongmin LEE ,  Bongjun KIM ,  Seungwon LEE ,  Hanwoong JUNG

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30036

Abstract: A system configured to perform an operation includes: a hardware device comprising a plurality of computing modules and a plurality of memory modules arranged in a lattice form, each of the computing modules comprising a coarse-grained reconfigurable array and each of the memory modules comprising a static random-access memory and a plurality of functional units connected to the static random-access memory; and a compiler configured to divide a target operation and assign the divided target operation to the computing modules and the memory modules such that the computing modules and the memory modules of the hardware device perform the target operation.

公开(公告)号：US20240112030A1

公开(公告)日：2024-04-04

申请号：US18529620

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhaeng LEE ,  Hyunsun PARK ,  Sehwan LEE ,  Seungwon LEE

IPC: G06N3/08 ,  G06N3/0495

CPC classification number: G06N3/08 ,  G06N3/0495

Abstract: A neural network method and apparatus is provided. A processor-implemented neural network method includes a processor and a memory storing information, including stored predetermined precision parameters of a layer of a n neural network, about the layer, the method includes obtaining information about the layer in the memory indicative of the number of output classes; determining, based on the obtained information, a precision for the layer based on the number of output classes of the layer, wherein the precision is determined proportionally with respect to the obtained number of output classes; and processing new parameters, with a set precision, for the layer based on the stored parameter.

公开(公告)号：US20230214652A1

公开(公告)日：2023-07-06

申请号：US18115978

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Seungwon LEE ,  Dongwoo LEE ,  Kiyoung CHOI ,  Sungbum KANG

IPC: G06N3/08 ,  G06N3/04 ,  G06F5/01 ,  G06F7/499 ,  G06F7/544

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06F5/01 ,  G06F7/49942 ,  G06F7/5443 ,  G06F2207/4824

Abstract: A processor-implemented data processing method includes encoding a plurality of weights of a filter of a neural network using an inverted two's complement fixed-point format; generating weight data based on values of the encoded weights corresponding to same filter positions of a plurality of filters; and performing an operation on the weight data and input activation data using a bit-serial scheme to control when to perform an activation function with respect to the weight data and input activation data.

公开(公告)号：US20220310194A1

公开(公告)日：2022-09-29

申请号：US17840722

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Joonho SONG ,  Seungwon LEE

IPC: G11C29/00 ,  G06F11/20 ,  G06F12/0815 ,  G11C29/38 ,  H01L25/065 ,  H01L25/18 ,  G01R31/3193

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

公开(公告)号：US20220179714A1

公开(公告)日：2022-06-09

申请号：US17467890

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanwoong JUNG ,  Joonho SONG ,  Seungwon LEE

IPC: G06F9/50 ,  G06F9/48 ,  G06N3/063

Abstract: A method and apparatus for scheduling a neural network operation. The method includes receiving data on a layer of a neural network, generating partitions to be assigned to cores by dividing the data, generating tiles by dividing the partitions, and scheduling an operation order of the tiles based on whether the data are shared between the cores.

公开(公告)号：US20220066660A1

公开(公告)日：2022-03-03

申请号：US17202591

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Hyunsoo KIM ,  Seungwon LEE ,  Yuhwan RO

IPC: G06F3/06 ,  G06N3/02 ,  G06F7/575

Abstract: A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.

公开(公告)号：US20210334618A1

公开(公告)日：2021-10-28

申请号：US17366908

申请日：2021-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongdo KIM ,  Sanghyo LEE ,  Seungwon LEE ,  Jongpil CHO

IPC: G06K19/077 ,  G06K19/07 ,  H02M1/08

Abstract: A smart card includes an antenna to transmit and to receive a radio frequency signal, a rectifier to rectify a signal received through the antenna to output a rectified voltage, a voltage regulator to operate in a first operation mode for stabilizing a level of the rectified voltage and a second operation mode for generating an internal voltage using the rectified voltage, a regulator converter to control the voltage regulator to operate the voltage regulator in one of the first operation and the second operation according to a mode selection signal, a clamp circuit to connect an output terminal of the rectifier to a ground according to the mode selection signal, a load modulator to vary a resistance of the antenna to perform a load modulation, and a regulator controller to generate the mode selection signal according to whether the load modulator is activated or deactivated.