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公开(公告)号：US20240103325A1
公开(公告)日：2024-03-28
申请号：US18218913
申请日：2023-07-06
发明人： Hyesung HAN , Bupmyoung Kim , Sungho Kim
IPC分类号： G02F1/1345
CPC分类号： G02F1/13452 , G02F2201/56
摘要： A display apparatus includes a display panel having a curvature, a plurality of chip-on-films connected to a side of the display panel, a first printed circuit board (PCB) connected to a first part of the plurality of chip-on-films, and a second PCB provided farther outside of the display panel than the first PCB from a center of the display panel, the second PCB being connected to a second part of the plurality of chip-on-films, and a number of chip-on-films of the second part of the plurality of chip-on-films is different than a number of chip-on-films of the first part of the plurality of chip-on-films.
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公开(公告)号：US20240086694A1
公开(公告)日：2024-03-14
申请号：US18508519
申请日：2023-11-14
发明人： Sungho Kim , Cheheung KIM , Jaeho LEE
摘要： A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.
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公开(公告)号：US11868870B2
公开(公告)日：2024-01-09
申请号：US16556424
申请日：2019-08-30
发明人： Sungho Kim , Cheheung Kim , Jaeho Lee
摘要： A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.
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公开(公告)号：US11817036B2
公开(公告)日：2023-11-14
申请号：US17838996
申请日：2022-06-13
发明人： Suhong Ko , Sungho Kim
IPC分类号： G09G3/20
CPC分类号： G09G3/2096 , G09G2310/04 , G09G2340/16 , G09G2354/00
摘要： A display apparatus is provided. The display apparatus includes a memory configured to store an input image, a display panel comprising a plurality of gate lines and a plurality of data lines, and a processor configured to control the display panel to output an entire area of a first frame of a plurality of frames included in the input image by controlling the plurality of gate lines and the plurality of data lines, and control the display panel to output a partial area of a second frame subsequent to the first frame by controlling some of the plurality of gate lines and the plurality of data lines.
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公开(公告)号：US20220392396A1
公开(公告)日：2022-12-08
申请号：US17838996
申请日：2022-06-13
发明人： Suhong Ko , Sungho Kim
IPC分类号： G09G3/20
摘要： A display apparatus is provided. The display apparatus includes a memory configured to store an input image, a display panel comprising a plurality of gate lines and a plurality of data lines, and a processor configured to control the display panel to output an entire area of a first frame of a plurality of frames included in the input image by controlling the plurality of gate lines and the plurality of data lines, and control the display panel to output a partial area of a second frame subsequent to the first frame by controlling some of the plurality of gate lines and the plurality of data lines.
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公开(公告)号：US11868874B2
公开(公告)日：2024-01-09
申请号：US18120137
申请日：2023-03-10
发明人： Sungho Kim , Cheheung Kim , Jaeho Lee
CPC分类号： G06N3/063 , G06F7/50 , G06F7/523 , G06F2207/4824
摘要： A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the first or second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform an arithmetic operation by using the operation values.
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公开(公告)号：US20230296933A1
公开(公告)日：2023-09-21
申请号：US18136514
申请日：2023-04-19
发明人： Enjung Kim , Jeongphil Seo , Sungho Kim , Seungjun Jeong , Suhong Ko , Bupmyoung Kim
IPC分类号： G02F1/1333 , G09G3/36 , G09G3/3208 , H01L27/12 , G02F1/1362 , G02F1/1345 , G02F1/1368 , G03F7/00
CPC分类号： G02F1/133308 , G02F1/13452 , G02F1/13456 , G02F1/136286 , G02F1/1368 , G03F7/0005 , G09G3/3208 , G09G3/36 , H01L27/124 , H01L27/1259 , G09G2310/0264
摘要： A display apparatus includes a first substrate including an upper end, a left end, a right end, and a lower end, and a plurality of wiring pads extending to the lower end; a display layer provided on a surface of the first substrate; a second substrate provided on a surface of the display layer, including an upper end, a left end, and a right end coincident with the upper end, the left end, and the right end of the first substrate, and a lower end shorter than the lower end of the first substrate, where the plurality of wiring pads of the first substrate are exposed; a plurality of side wiring pads provided on the lower end of the first substrate and the lower end of the second substrate and connected to the plurality of wiring pads; and a display driving circuit connected to the plurality of side wiring pads.
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18.发明授权公开(公告)号：US11531870B2
公开(公告)日：2022-12-20
申请号：US16557182
申请日：2019-08-30
发明人： Sungho Kim , Cheheung Kim , Jaeho Lee
摘要： A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.
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