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1.
公开(公告)号:US11853869B2
公开(公告)日:2023-12-26
申请号:US17987369
申请日:2022-11-15
发明人: Sungho Kim , Cheheung Kim , Jaeho Lee
摘要: A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.
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公开(公告)号:US11663451B2
公开(公告)日:2023-05-30
申请号:US16274547
申请日:2019-02-13
发明人: Sungho Kim , Cheheung Kim , Jaeho Lee
CPC分类号: G06N3/063 , G06F7/50 , G06F7/523 , G06F2207/4824
摘要: A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform a multi-bit operation by using the operation values and the time information.
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公开(公告)号:US12105371B2
公开(公告)日:2024-10-01
申请号:US17994120
申请日:2022-11-25
发明人: Naewon Jang , Kihyung Kang , Sungho Kim , Sanghyun Sohn
IPC分类号: G02F1/1335 , G02F1/1333 , G02F1/13363
CPC分类号: G02F1/133504 , G02F1/133531 , G02F1/13363 , G02F1/133345 , G02F1/133528
摘要: A display apparatus includes a display panel including a first optical film. The first optical film includes: a biaxially elongated polyethylene terephthalate (PET) film; a scattering layer provided on the biaxially elongated PET film and having a haze value between 40% and 60%, the haze value representing a scattering rate of light; and a low-reflective layer provided on the scattering layer.
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4.
公开(公告)号:US20240288734A1
公开(公告)日:2024-08-29
申请号:US18391148
申请日:2023-12-20
发明人: Bupmyoung KIM , Sungho Kim
IPC分类号: G02F1/1345 , H01L27/12
CPC分类号: G02F1/13452 , H01L27/124 , G02F1/136286 , G02F1/1368 , H01L23/5387
摘要: A display apparatus includes a substrate including an active area including a plurality of pixels, and an outer lead bonding (OLB) area; a first Chip On Film (COF) coupled to the OLB area; a second COF coupled to the OLB area and adjacent to the first COF; a first printed circuit board (PCB) coupled to the first COF; and a second PCB coupled to the second COF, wherein the OLB area may include a first area to which the first COF is coupled, a second area to which the second COF is coupled, and a dummy area between the first area and the second area, and the dummy area may include a conductive pattern electrically connecting the first COF and the second COF.
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公开(公告)号:US11754876B2
公开(公告)日:2023-09-12
申请号:US17716722
申请日:2022-04-08
发明人: Bupmyoung Kim , Sungho Kim
IPC分类号: G02F1/13357 , G02F1/1335
CPC分类号: G02F1/133603 , G02F1/133607 , G02F1/133608 , G02F1/133612
摘要: A display apparatus includes: a display panel; a light source module provided behind the display panel, the light source module including a board and a light source provided on a rear surface of the board; a rear chassis covering a rear surface of the light source module; and a supporter extending between the board and the rear chassis, the supporter being electrically conductive.
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公开(公告)号:US11681899B2
公开(公告)日:2023-06-20
申请号:US16561378
申请日:2019-09-05
发明人: Sungho Kim , Yulhwa Kim , Hyungjun Kim , Jae-Joon Kim , Jinseok Kim
摘要: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
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公开(公告)号:US20230244099A1
公开(公告)日:2023-08-03
申请号:US17994120
申请日:2022-11-25
发明人: Naewon JANG , Kihyung Kang , Sungho Kim , Sanghyun Sohn
IPC分类号: G02F1/1335 , G02F1/13363
CPC分类号: G02F1/133504 , G02F1/133531 , G02F1/13363
摘要: A display apparatus includes a display panel including a first optical film. The first optical film includes: a biaxially elongated polyethylene terephthalate (PET) film; a scattering layer provided on the biaxially elongated PET film and having a haze value between 40% and 60%, the haze value representing a scattering rate of light; and a low-reflective layer provided on the scattering layer.
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公开(公告)号:US11567359B2
公开(公告)日:2023-01-31
申请号:US17212490
申请日:2021-03-25
发明人: Sungho Choi , Sungho Kim , Jeongphil Seo , Junghyun Yoon , Minnyeong Han
IPC分类号: G02F1/1335 , G02F1/1333 , G02F1/1339
摘要: A display panel and a display apparatus are provided. The display panel may include a first glass substrate; a second glass substrate provided in front of the first glass substrate in a first direction; and a color filter layer provided between the second glass substrate and the first glass substrate in the first direction. The color filter layer may include a plurality of color filters and a black matrix surrounding the plurality of color filters. A side edge of the black matrix may extend beyond a side edge of the first glass substrate in a second direction that is orthogonal to the first direction. The display apparatus may include a backlight unit and the display panel.
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公开(公告)号:US11521046B2
公开(公告)日:2022-12-06
申请号:US16170081
申请日:2018-10-25
发明人: Sungho Kim , Jinseok Kim , Yulhwa Kim , Jaejoon Kim , Dusik Park , Hyungjun Kim
摘要: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.
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公开(公告)号:US12130510B2
公开(公告)日:2024-10-29
申请号:US18136514
申请日:2023-04-19
发明人: Enjung Kim , Jeongphil Seo , Sungho Kim , Seungjun Jeong , Suhong Ko , Bupmyoung Kim
IPC分类号: G02F1/1333 , G02F1/1345 , G02F1/1362 , G02F1/1368 , G03F7/00 , G09G3/3208 , G09G3/36 , H01L27/12
CPC分类号: G02F1/133308 , G02F1/13452 , G02F1/13456 , G02F1/136286 , G02F1/1368 , G03F7/0005 , G09G3/3208 , G09G3/36 , H01L27/124 , H01L27/1259 , G09G2310/0264
摘要: A display apparatus includes a first substrate including an upper end, a left end, a right end, and a lower end, and a plurality of wiring pads extending to the lower end; a display layer provided on a surface of the first substrate; a second substrate provided on a surface of the display layer, including an upper end, a left end, and a right end coincident with the upper end, the left end, and the right end of the first substrate, and a lower end shorter than the lower end of the first substrate, where the plurality of wiring pads of the first substrate are exposed; a plurality of side wiring pads provided on the lower end of the first substrate and the lower end of the second substrate and connected to the plurality of wiring pads; and a display driving circuit connected to the plurality of side wiring pads.
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