公开(公告)号：US11081192B2

公开(公告)日：2021-08-03

申请号：US16668949

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

IPC: G11C16/32 ,  G11C16/26

Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.

公开(公告)号：US10991429B2

公开(公告)日：2021-04-27

申请号：US16891603

申请日：2020-06-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Fumiaki Toyama ,  Takuya Ariki

IPC: G11C16/08 ,  G11C5/02 ,  H01L27/11565 ,  H01L27/11575 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C8/10

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

公开(公告)号：US10984874B1

公开(公告)日：2021-04-20

申请号：US16681968

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Naoki Ookuma ,  Toru Miwa

IPC: G11C16/28 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11582

Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.

公开(公告)号：US10720213B2

公开(公告)日：2020-07-21

申请号：US15780607

申请日：2016-12-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Fumiaki Toyama ,  Takuya Ariki

IPC: G11C16/08 ,  G11C5/02 ,  H01L27/11565 ,  H01L27/11575 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C8/10

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.