公开(公告)号：US20210142858A1

公开(公告)日：2021-05-13

申请号：US16681968

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Naoki Ookuma ,  Toru Miwa

IPC: G11C16/28 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/04

Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.

公开(公告)号：US20200185397A1

公开(公告)日：2020-06-11

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20190057741A1

公开(公告)日：2019-02-21

申请号：US15780607

申请日：2016-12-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki OGAWA ,  Fumiaki Toyama ,  Takuya Ariki

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11575 ,  G11C5/02 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L27/1157 ,  G11C8/10

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

公开(公告)号：US20210134375A1

公开(公告)日：2021-05-06

申请号：US16668949

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

IPC: G11C16/32 ,  G11C16/26

Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.

公开(公告)号：US10885984B1

公开(公告)日：2021-01-05

申请号：US16668073

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

IPC: G11C16/04 ,  G11C16/14 ,  H01L27/11524

Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.

公开(公告)号：US10734080B2

公开(公告)日：2020-08-04

申请号：US16213382

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11526 ,  G11C16/14 ,  G11C16/10

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20200185039A1

公开(公告)日：2020-06-11

申请号：US16213382

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20210134828A1

公开(公告)日：2021-05-06

申请号：US16675800

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Naoki Ookuma ,  Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573

Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

公开(公告)号：US10854619B2

公开(公告)日：2020-12-01

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  H01L27/11526

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US11177277B2

公开(公告)日：2021-11-16

申请号：US16675800

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Naoki Ookuma ,  Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027

Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.