公开(公告)号：US12193236B2

公开(公告)日：2025-01-07

申请号：US17772280

申请日：2020-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Satoru Ohshita ,  Kazuki Tsuda ,  Tatsuya Onuki

IPC: H10B43/40 ,  G11C16/08 ,  H10B43/27

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

公开(公告)号：US12156410B2

公开(公告)日：2024-11-26

申请号：US17629804

申请日：2020-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Tatsuya Onuki ,  Yuki Okamoto ,  Hideki Uochi ,  Satoru Okamoto ,  Hiromichi Godo ,  Kazuki Tsuda ,  Hitoshi Kunitake

IPC: H10B63/00 ,  H10B41/27 ,  H10B43/27

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US11921919B2

公开(公告)日：2024-03-05

申请号：US17671905

申请日：2022-02-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Kouhei Toyotaka ,  Kazuki Tsuda ,  Satoru Ohshita ,  Hidefumi Rikimaru

IPC: G06F3/01 ,  G02B27/01 ,  G09G3/00 ,  G09G3/3225 ,  H10K59/121 ,  H01L27/12 ,  H01L29/786

CPC classification number: G06F3/013 ,  G02B27/0172 ,  G09G3/002 ,  G09G3/3225 ,  H10K59/1213 ,  G02B2027/0178 ,  G09G2354/00 ,  G09G2360/14 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.

公开(公告)号：US11594176B2

公开(公告)日：2023-02-28

申请号：US17686796

申请日：2022-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi Godo ,  Yoshiyuki Kurokawa ,  Kazuki Tsuda ,  Satoru Ohshita ,  Hidefumi Rikimaru

IPC: G09G3/3208 ,  H01L27/32 ,  H01L29/786

Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.