公开(公告)号：US20150069384A1

公开(公告)日：2015-03-12

申请号：US14474533

申请日：2014-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KOBAYASHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78696

Abstract: A semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with side surfaces of the first oxide semiconductor film, side surfaces of the second oxide semiconductor film, and the top surface of the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the top surface of the gate insulating film. A length obtained by subtracting a channel length between the source electrode and the drain electrode from a length of the second oxide semiconductor film in the channel length direction is 0.2 times to 2.0 times as long as the channel length.

Abstract translation: 半导体器件包括绝缘表面上的第一氧化物半导体膜; 第一氧化物半导体膜上的第二氧化物半导体膜; 与第一氧化物半导体膜的侧表面，第二氧化物半导体膜的侧表面和第二氧化物半导体膜的顶表面接触的源电极和漏电极; 第二氧化物半导体膜上的第三氧化物半导体膜，源电极和漏电极; 第三氧化物半导体膜上的栅极绝缘膜; 以及与栅极绝缘膜的顶表面接触的栅电极。 通过从沟道长度方向上的第二氧化物半导体膜的长度减去源电极和漏电极之间的沟道长度而获得的长度是沟道长度的0.2倍至2.0倍。

公开(公告)号：US20150021596A1

公开(公告)日：2015-01-22

申请号：US14330444

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L27/1225 ,  H01L29/0684 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.

Abstract translation: 半导体器件在绝缘表面上设置有第一氧化物半导体膜; 第一氧化物半导体膜上的第二氧化物半导体膜; 与所述绝缘表面的顶表面接触的第三氧化物半导体膜，所述第一氧化物半导体膜的侧表面以及所述第二氧化物半导体膜的侧表面和顶表面; 第三氧化物半导体膜上的栅极绝缘膜; 以及与栅极绝缘膜接触并与第二氧化物半导体膜的顶表面和侧表面a相对的栅电极。 第一氧化物半导体膜的厚度大于第三氧化物半导体膜的厚度与栅极绝缘膜的厚度的和，并且该差值大于或等于20nm。

公开(公告)号：US20210328074A1

公开(公告)日：2021-10-21

申请号：US17358051

申请日：2021-06-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KOBAYASHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24

Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.

公开(公告)号：US20170309750A1

公开(公告)日：2017-10-26

申请号：US15644940

申请日：2017-07-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KOBAYASHI ,  Shinpei MATSUDA ,  Daisuke MATSUBAYASHI ,  Hiroyuki TOMISU

IPC: H01L29/786 ,  H01L27/06 ,  G02F1/1368 ,  H01L21/822 ,  H01L29/04

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2201/58 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/045 ,  H01L29/78696

Abstract: A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface.

公开(公告)号：US20170263774A1

公开(公告)日：2017-09-14

申请号：US15604934

申请日：2017-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shuhei NAGATSUKA ,  Yutaka SHIONOIRI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

公开(公告)号：US20170005202A1

公开(公告)日：2017-01-05

申请号：US15264667

申请日：2016-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KOBAYASHI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/0629 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/78696

Abstract: A semiconductor device having stable electric characteristics is provided. The transistor includes first to third oxide semiconductor layers, a gate electrode, and a gate insulating layer. The second oxide semiconductor layer has a portion positioned between the first and third oxide semiconductor layers. The gate insulating layer has a region in contact with a top surface of the third oxide semiconductor layer. The gate electrode overlaps with a top surface of the portion with the gate insulating layer positioned therebetween. The gate electrode faces a side surface of the portion in a channel width direction with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 8 nm. The length in the channel width direction of the second oxide semiconductor layer is less than 60 nm.

Abstract translation: 提供具有稳定电特性的半导体器件。 晶体管包括第一至第三氧化物半导体层，栅电极和栅极绝缘层。 第二氧化物半导体层具有位于第一和第三氧化物半导体层之间的部分。 栅极绝缘层具有与第三氧化物半导体层的顶表面接触的区域。 栅电极与栅绝缘层位于其间的部分的顶表面重叠。 栅极电极在栅极绝缘层位于沟槽宽度方向上面对该部分的侧面。 第二氧化物半导体层包括厚度大于或等于2nm且小于8nm的区域。 第二氧化物半导体层的沟道宽度方向的长度小于60nm。