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公开(公告)号:US20230054492A1
公开(公告)日:2023-02-23
申请号:US17797494
申请日:2020-02-14
Applicant: Sharp Kabushiki Kaisha
Inventor: Kaoru YAMAMOTO
IPC: G09G3/3233 , G09G3/20
Abstract: In a display device having an external compensation function, a decrease in compensation accuracy caused by coupling noise generated in a data signal line is prevented. A source driver includes an integration circuit that measures a current corresponding to the characteristic of a drive transistor. An emission driver applies a light-emission control signal to each light-emission control line on the basis of a plurality of light-emission control clock signals (ECK1 to ECK4) outputted from a display control circuit. In a current measurement period, the flow of a current corresponding to the characteristic of the drive transistor into the integration circuit is stopped at an edge timing, which is a timing at which the level of at least one of the plurality of light-emission control clock signals (ECK1 to ECK4) changes.
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公开(公告)号:US20170186373A1
公开(公告)日:2017-06-29
申请号:US15316921
申请日:2015-06-05
Applicant: Sharp Kabushiki Kaisha
Inventor: Daichi NISHIKAWA , Yasuyuki OGAWA , Kaoru YAMAMOTO , Noritaka KISHI , Shigetsugu YAMANAKA , Masanori OHARA , Noboru NOGUCHI
IPC: G09G3/3258 , G09G3/3291 , G11C19/28 , G09G3/3266
CPC classification number: G09G3/3258 , G09G3/3233 , G09G3/3266 , G09G3/3291 , G09G2300/0842 , G09G2310/0286 , G09G2310/065 , G09G2310/08 , G09G2320/0285 , G09G2320/0295 , G09G2320/045 , G09G2320/048 , G09G2330/023 , G09G2330/12 , G11C19/28
Abstract: In a current measurement period set in a pause period, a display device of the present invention applies measurement voltages to data lines (S1 to Sm) and measures currents outputted to monitoring lines (M1 to Mm) from m pixel circuits (18), and then applies data voltages generated corresponding to video signals to the data lines (S1 to Sm).
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公开(公告)号:US20190304396A1
公开(公告)日:2019-10-03
申请号:US16365801
申请日:2019-03-27
Applicant: Sharp Kabushiki Kaisha
Inventor: Kaoru YAMAMOTO
Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region. Each unit circuit in the demultiplexer circuit includes n switching TFTs. The demultiplexer circuit includes a boost circuit capable of boosting a voltage applied to a gate electrode of the switching TFT. The boost circuit includes a set unit configured to perform a set action, a boost unit configured to perform a boost action, and a reset unit configured to perform a reset action. The set unit includes a setting TFT including a drain electrode connected to the drive signal line and a source electrode connected to a node connected to the gate electrode of the switching TFT. When the set unit performs the set action, a first signal voltage is supplied from the drive signal line to the drain electrode of the setting TFT, and a second signal voltage higher than the first signal voltage is supplied to the gate electrode of the setting TFT.
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公开(公告)号:US20190250448A1
公开(公告)日:2019-08-15
申请号:US16329240
申请日:2017-08-28
Applicant: Sharp Kabushiki Kaisha
Inventor: Kaoru YAMAMOTO
IPC: G02F1/1345 , G02F1/1368 , G02F1/1362
CPC classification number: G02F1/13452 , G02F1/133 , G02F1/136286 , G02F1/1368 , G02F2202/104 , G09G3/20 , G09G3/36
Abstract: Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.
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公开(公告)号:US20190228828A1
公开(公告)日:2019-07-25
申请号:US16330219
申请日:2017-08-28
Applicant: Sharp Kabushiki Kaisha
Inventor: Kaoru YAMAMOTO
IPC: G11C17/06 , H01L27/105 , H01L29/786 , H01L49/02
Abstract: Provided is a semiconductor device having a plurality of memory cells (MC1 and MC2), in which each of the plurality of memory cells (MC1 and MC2) includes: a memory transistor (10M) having an oxide semiconductor layer (17M) as an active layer; and a first selection transistor (10S) having a crystalline silicon layer (13S) as the active layer and connected to the memory transistor (10M) in series.
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公开(公告)号:US20180342208A1
公开(公告)日:2018-11-29
申请号:US16052669
申请日:2018-08-02
Applicant: Sharp Kabushiki Kaisha
Inventor: Daichi NISHIKAWA , Yasuyuki OGAWA , Kaoru YAMAMOTO , Noritaka KISHI , Shigetsugu YAMANAKA , Masanori OHARA , Noboru NOGUCHI
IPC: G09G3/3258 , G09G3/3266 , G11C19/28 , G09G3/3233 , G09G3/3291
CPC classification number: G09G3/3258 , G09G3/3233 , G09G3/3266 , G09G3/3291 , G09G2300/0842 , G09G2310/0286 , G09G2310/065 , G09G2310/08 , G09G2320/0285 , G09G2320/0295 , G09G2320/045 , G09G2320/048 , G09G2330/023 , G09G2330/12 , G11C19/28
Abstract: In a current measurement period set in a pause period, a display device of the present invention applies measurement voltages to data lines (S1 to Sm) and measures currents outputted to monitoring lines (M1 to Mm) from m pixel circuits (18), and then applies data voltages generated corresponding to video signals to the data lines (S1 to Sm).
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公开(公告)号:US20160063955A1
公开(公告)日:2016-03-03
申请号:US14783548
申请日:2014-02-25
Applicant: SHARP KABUSHIKI KAISHA
Inventor: Kaoru YAMAMOTO , Yasuyuki OGAWA , Akihiro ODA , Masahiro TOMIDA
IPC: G09G5/10
CPC classification number: G09G5/10 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G09G2330/022 , G09G2330/027 , H03K3/356026
Abstract: A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.
Abstract translation: 显示装置包括:显示单元,驱动单元和控制单元。 显示单元包括以矩阵形式布置的多个像素单元。 驱动器单元包括输出晶体管,其被配置为驱动连接到多个像素单元的多条扫描线。 控制单元被配置为在显示周期中向驱动器单元供应用于在显示单元上显示图像的信号,并且在显示暂停时段中控制输出晶体管的偏置状态,使得阈值的绝对值 在显示周期中增加的输出晶体管的电压降低。
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