公开(公告)号：US20190305071A1

公开(公告)日：2019-10-03

申请号：US16365799

申请日：2019-03-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO

IPC: H01L27/32 ,  G09G3/3225 ,  H01L27/12

Abstract: An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region, and a power source circuit configured to supply power source voltages at a plurality of levels to the demultiplexer circuit. The demultiplexer circuit includes a boost circuit configured to increase a voltage to be applied to a gate electrode of a switching TFT. The boost circuit includes a set up unit to be driven by a first drive signal to pre-charge a node coupled to the gate electrode, a reset unit to be driven by a second drive signal to reset a potential of the node, and a boost unit to be driven by a third drive signal to increase the potential of the node pre-charged by the set up unit. An amplitude of the first drive signal and an amplitude of the second drive signal are identical to each other. An amplitude of the third drive signal differs from the amplitudes of the first drive signal and the second drive signal.

公开(公告)号：US20180108309A1

公开(公告)日：2018-04-19

申请号：US15318043

申请日：2015-06-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Kohhei TANAKA ,  Takeshi NOMA ,  Takayuki NISHIYAMA ,  Ryo YONEBAYASHI ,  Yasuyuki OGAWA ,  Kaoru YAMAMOTO

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

Abstract: Each driving circuit in a shift register includes an output unit, a precharge unit, a boosting unit, a gate voltage discharge unit, a gate line discharge unit, and an internal line netA. The output unit includes a TFT(F) that outputs a selection voltage to a gate line. The precharge unit includes a TFT(B) that outputs a control voltage for causing the TFT in the output unit to operate. The boosting unit boosts up a gate voltage of the TFT in the output unit through a capacitor (Cbst). The gate voltage discharge unit includes a TFT(K) that pulls down this gate voltage during a non-selection period while the gate line is not selected. The gate line discharge unit includes a TFT(L) that outputs a non-selection voltage to the gate line during the non-selection period while the gate line is not selected. The internal line is connected to a gate terminal of the TFT in the output unit, the precharge unit, the gate voltage discharge unit, and the boosting unit. A gate terminal of at least one of the TFTs in the precharge unit, the gate voltage discharge unit, and the gate line discharge unit is connected to an internal line in another driving circuit.

公开(公告)号：US20210110781A1

公开(公告)日：2021-04-15

申请号：US16603597

申请日：2018-04-05

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343

Abstract: An active matrix substrate according to an embodiment of the present invention includes: a plurality of source bus lines provided on a substrate; a source driver disposed in a peripheral region; signal output lines each connected to a corresponding one of output terminals of the source driver; and a demultiplexer circuit disposed in a peripheral region. The demultiplexer circuit includes unit circuits each configured to distribute a display signal from one signal output line to n source bus lines (n is an integer larger than or equal to 2). Each unit circuit includes n switching TFTs configured to perform individual on/off control of electrical connections of the n branch lines to the n source bus lines. The n branch lines being connected to one signal output lines. The demultiplexer circuit further includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the n switching TFTs.

公开(公告)号：US20200211489A1

公开(公告)日：2020-07-02

申请号：US16642090

申请日：2018-08-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO

IPC: G09G3/36

Abstract: The active matrix substrate includes a demultiplexer circuit disposed in a peripheral region. Unit circuits of the demultiplexer circuit each distribute a display signal from one signal output line to n source bus lines (n: two or greater). Each unit circuit includes n branch lines and n switching TFTs configured to perform individual on/off control of electrical connections of the branch lines to the source bus lines. The demultiplexer circuit includes a plurality of boost circuits each configured to boost a voltage applied to a gate electrode of a corresponding one of the switching TFTs. Each boost circuit includes: a set-and-reset unit configured to perform set operation of pre-charging a node connected to the gate electrode and reset operation of resetting the potential of the node at different timings; and a boost unit configured to perform boost operation of boosting the potential of the node pre-charged by the set operation.

公开(公告)号：US20220392403A1

公开(公告)日：2022-12-08

申请号：US17642785

申请日：2019-09-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275

Abstract: A display device that includes pixel circuits, in each of which a plurality of types of transistors coexist, and that operates normally is implemented while suppressing an increase in processing cost.
Each unit circuit includes a first control circuit (311), a first output circuit (321), and a second output circuit (322). The first output circuit (321) includes a first output terminal (38) connected to a first scanning signal line; a P-type transistor (M4) having a control terminal connected to a first internal node (N1), a first conductive terminal to which a gate high potential (VGH) is provided, and a second conductive terminal connected to the first output terminal (38); and a N-type transistor (M5) having a control terminal connected to the first internal node (N1), a first conductive terminal connected to the first output terminal (38), and a second conductive terminal to which a gate low potential (VGL) is provided.

公开(公告)号：US20190079330A1

公开(公告)日：2019-03-14

申请号：US16123045

申请日：2018-09-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO ,  Akihiro ODA ,  Tadayoshi MIYAMOTO

IPC: G02F1/1345 ,  G02F1/1343 ,  G02F1/1333 ,  G09G3/36 ,  H01L27/12

Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.

公开(公告)号：US20170323612A1

公开(公告)日：2017-11-09

申请号：US15522425

申请日：2015-10-23

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO ,  Yasuyuki OGAWA

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0871 ,  G09G2310/0208 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28

Abstract: In a forward shift operation, a second input signal having a higher voltage than a voltage of a first input signal is input to a second gate terminal in a case that a first gate terminal of a first transistor is charged, and a fourth input signal having a higher voltage than a voltage of a third input signal is input to a third gate terminal in a case that the first gate terminal of the first transistor is discharged. In a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

公开(公告)号：US20160372068A1

公开(公告)日：2016-12-22

申请号：US14901461

申请日：2014-02-25

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Kaoru YAMAMOTO ,  Yasuyuki OGAWA

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/20 ,  G09G2310/0251 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28

Abstract: A unit shift register circuit constitutes each stage of a shift register circuit. The unit shift register circuit includes an output transistor (T1) configured to input a prescribed clock signal (CK) to a drain terminal, and output an output signal (OUT) from a source terminal. The unit shift register circuit includes a setting transistor (T2) in which a source terminal is connected to a gate electrode of the output transistor (T1), is configured to input an input signal (S) to the drain terminal, and is configured to input to a gate electrode an input signal (VS) in a case of charging a gate electrode (node (VC)) of the output transistor (T1). The input signal (VS) having a voltage higher than that of the input signal (S).

Abstract translation: 单元移位寄存器电路构成移位寄存器电路的每一级。 单元移位寄存器电路包括被配置为向漏极端子输入规定的时钟信号（CK）的输出晶体管（T1），并从源极端子输出输出信号（OUT）。 单元移位寄存器电路包括其中源极端子连接到输出晶体管（T1）的栅电极的设置晶体管（T2），被配置为向漏极端子输入输入信号（S），并且被配置为 在对输出晶体管（T1）的栅电极（节点（VC））充电的情况下，向栅电极输入输入信号（VS）。 输入信号（VS）的电压高于输入信号（S）的电压。

公开(公告)号：US20160042806A1

公开(公告)日：2016-02-11

申请号：US14774558

申请日：2014-02-12

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yasuyuki OGAWA ,  Kaoru YAMAMOTO ,  Akihiro ODA ,  Masahiro TOMIDA

IPC: G11C19/28 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/043

Abstract: A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.

Abstract translation: 移位寄存器电路具有彼此级联的多个单位电路，并且根据时钟信号输出接收到的脉冲信号作为输出信号，移位寄存器电路顺次地输出来自多个单元电路的输出信号 。 输出电路各自包括双栅极晶体管，其具有控制漏电极和源电极之间的导电性的第一栅电极，以及通过绝缘层形成的第二栅电极，并且设置成跨越第一栅电极跨越半导体层 漏电极和源电极。 移位寄存器电路根据施加到第一栅电极的电压向第二栅电极施加规定的电压。

公开(公告)号：US20230057970A1

公开(公告)日：2023-02-23

申请号：US17797493

申请日：2020-02-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO

IPC: G09G3/3233

Abstract: In a display device having an external compensation function, a decrease in compensation accuracy caused by coupling noise generated in a data signal line is prevented. An emission driver that applies a light-emission control signal (EM) to each of a plurality of light-emission control lines includes a shift register formed of a plurality of unit circuits. The shift register generates a light-emission control signal (EM) to be applied to each light-emission control line on the basis of a plurality of light-emission control clock signals (ECK1 to ECK4) outputted from a display control circuit. The display control circuit stops the outputs of the plurality of light-emission control clock signals (ECK1 to ECK4) throughout a current measurement period in which a current corresponding to the characteristic of the drive transistor is measured.