公开(公告)号：US09501373B2

公开(公告)日：2016-11-22

申请号：US14631329

申请日：2015-02-25

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/10 ,  G06F11/07

CPC classification number: G06F11/2017 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0238 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7204 ,  G06F2212/7208 ,  G11C29/70 ,  G11C2029/0409

Abstract: A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super page by selecting main pages from the respective main regions, wherein when a main page of a main region in a memory device is a bad region, the processor forms a virtual super page by selecting a virtual page from a virtual region in the memory device instead of the main page.

Abstract translation: 一种数据存储装置，包括各自的主区域和各自的虚拟区域的存储装置，以及适于通过从各个主要区域选择主页形成超级页面的处理器，其中当存储装置中的主要区域的主页是 处理器通过从存储设备中的虚拟区域而不是主页面中选择虚拟页面来形成虚拟超级页面。

公开(公告)号：US12066928B2

公开(公告)日：2024-08-20

申请号：US18151320

申请日：2023-01-06

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0238 ,  G06F13/1673 ,  G06F2212/7201

Abstract: A memory system that includes a system protection function implemented by using a double-map scheme, a memory controller, and operation methods thereof are disclosed. The memory system includes a memory device and a memory controller. The memory device includes a plurality of nonvolatile memory cells corresponding to a plurality of physical addresses respectively. The memory controller controls the memory device and uses a first map and a second map. The first map includes physical address mapping information based on a logical address for a physical address where first-type data is stored. The second map includes physical address mapping information based on a logical address for a physical address where second-type data is stored.

公开(公告)号：US11561712B2

公开(公告)日：2023-01-24

申请号：US17238848

申请日：2021-04-23

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06 ,  G06F12/0802

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved physical address obtainment speed may include a nonvolatile memory device configured to store map data including a plurality of map segments including mapping information and, a volatile memory device including a first map cache area temporarily storing the map data configured by map entries each corresponding to one logical address, and a second map cache area temporarily storing the map data configured by map indexes each corresponding to a plurality of logical addresses.

公开(公告)号：US11550662B2

公开(公告)日：2023-01-10

申请号：US17348462

申请日：2021-06-15

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F11/10 ,  G06F9/4401 ,  G06F12/10

Abstract: The present technology relates to an electronic device. More specifically, the present technology relates to a storage device and a computing system. A storage device according to an embodiment may include a memory device including a firmware block group configured to store main firmware data and sub firmware data, and a user block group configured to store write data, and a memory controller, in response to a booting request provided from a host, configured to count a number of previously generated power losses based on data stored in an open block in the user block group in a booted state based on the main firmware data, performs a rebooting operation using the sub firmware data when the number of power losses exceeds a reference number, and execute sub firmware to correct an error of data related to the power losses.

公开(公告)号：US11416366B2

公开(公告)日：2022-08-16

申请号：US16719055

申请日：2019-12-18

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/00 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42

Abstract: There are provided a controller and a memory system having the same. The controller includes: a background operation manager configured to determine a background operation level according to an amount of first data received from a host and an amount of second data generated in a randomization operation and an error check operation of the first data, and output a background operation signal according to the background operation level, and a processor configured to output a background command set by adjusting an operating ratio of a background operation according to the background operation signal.

公开(公告)号：US11360886B2

公开(公告)日：2022-06-14

申请号：US16925181

申请日：2020-07-09

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/02 ,  G06F12/08 ,  G06F9/30 ,  G06F3/06 ,  G06F12/06 ,  G11C11/56 ,  G06F12/0811 ,  G06F12/0891

Abstract: A storage device having an improved write response speed includes a memory device and a memory controller. The memory device including a plurality of turbo write blocks and a plurality of normal memory blocks and a memory controller configured to control the memory device to store data corresponding to a write request received from a host in any one block among the plurality of turbo write blocks and the plurality of normal memory blocks, in response to the write request, wherein the plurality of turbo write blocks respectively include memory cells being programmed to store different numbers of data bits.

公开(公告)号：US11216384B2

公开(公告)日：2022-01-04

申请号：US16674968

申请日：2019-11-05

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/02

Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device may include receiving a read command from a host; determining whether changed L2P map data corresponding to L2P map data included in the read command is registered in a dirty list; and performing, when the changed L2P map data is determined as registered in the dirty list, a read operation on the nonvolatile memory device based on the changed L2P map data among L2P map data included in a plurality of L2P segments.

公开(公告)号：US11163696B2

公开(公告)日：2021-11-02

申请号：US16595013

申请日：2019-10-07

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/02 ,  G06F12/10

Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In an embodiment of the present disclosure, a controller for controlling a nonvolatile memory device may perform a sync-up operation of transmitting a logical-to-physical (L2P) map segment to a host to update the L2P map segment stored in a host memory included in the host when a map data changing event occurs, register the L2P map segment transmitted to the host and time information at which the sync-up operation is performed in a sync-up management list, calculate a sync-up period based on the time information, and perform the sync-up operation on an L2P map segment having a sync-up period greater than a threshold time, among L2P map segments registered in the sync-up management list.

公开(公告)号：US20210255961A1

公开(公告)日：2021-08-19

申请号：US16936779

申请日：2020-07-23

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/1009

Abstract: A memory system is provided to include a first storage device including a first memory device and a first memory controller configured to receive, from a host external to the first storage device, a request including a logical address corresponding to the request; and a second storage device including a second memory device and a second memory controller coupled to receive a request from the first storage device and to control the second memory device, wherein the first memory controller is configured to select a target address among candidate addresses and map the logical address received from the host to the target address, and wherein the candidate addresses include first physical addresses corresponding to the first memory blocks and virtual addresses corresponding to the second memory blocks included in the second memory device.

公开(公告)号：US11061815B2

公开(公告)日：2021-07-13

申请号：US16774287

申请日：2020-01-28

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/02 ,  G06F13/16 ,  G06F9/30 ,  G06F9/54

Abstract: A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance.