公开(公告)号：US12189526B2

公开(公告)日：2025-01-07

申请号：US18507963

申请日：2023-11-13

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/02 ,  G06F12/0891

Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.

公开(公告)号：US11385997B2

公开(公告)日：2022-07-12

申请号：US16690643

申请日：2019-11-21

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0871 ,  G06F11/07 ,  G06F3/06

Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes a read counter configured to store a block read count value of a super block and memory blocks within a non-super block as a status information in an internal memory by counting a number of times that a read operation is performed on the memory blocks; and a super block manager configured to: store a super block reclaim trigger reference and a non-super block reclaim trigger reference, which is set for the super block and the non-super block, as the status information in the internal memory, divide data stored in the memory blocks into hot data and cold data according to the block read count value, and copy the hot data in the non-super block to the super block according to the status information.

公开(公告)号：US11061815B2

公开(公告)日：2021-07-13

申请号：US16774287

申请日：2020-01-28

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/02 ,  G06F13/16 ,  G06F9/30 ,  G06F9/54

Abstract: A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance.

公开(公告)号：US11036629B2

公开(公告)日：2021-06-15

申请号：US16729198

申请日：2019-12-27

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0808 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0882

Abstract: In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.

公开(公告)号：US12298905B2

公开(公告)日：2025-05-13

申请号：US18352870

申请日：2023-07-14

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0864

Abstract: A storage device may determine a target data segment from among a plurality of data segments, execute a hash function on the target data segment, and cache the target data segment in a data segment cache based on a result of executing the hash function on the target data segment. The data segment cache may be a hash table including N buckets each of which is able to cache one or more data segments. The hash function may be a function which outputs an index of the target bucket based on N, an index of the target data segment, and a seed value.

公开(公告)号：US12287972B2

公开(公告)日：2025-04-29

申请号：US17942517

申请日：2022-09-12

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

Abstract: A memory controller includes: a program operation controller configured to control a memory device to store data and individual mapping information; a mapping information storage configured to store therein mapping information; a mapping information update controller configured to control the memory device to store the mapping information in a second memory block; perform an update operation of updating the mapping information, and delay, when sequentiality of a predetermined number or more of logical addresses is maintained with respect to the predetermined time, the update operation until the sequentiality is broken; and a Sudden Power Off Recovery (SPOR) controller configured to receive the individual mapping information, recover the mapping information for the data stored in the page during a delay section and provide the recovered mapping information to the mapping information storage.

公开(公告)号：US11960765B2

公开(公告)日：2024-04-16

申请号：US17532789

申请日：2021-11-22

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0673

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

公开(公告)号：US11847332B2

公开(公告)日：2023-12-19

申请号：US17516392

申请日：2021-11-01

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: A data storage apparatus includes storage including a plurality of memory blocks and a controller configured to set an attribute of each of the memory blocks as a random memory block or a sequential memory block, and to manage validity of map data for data stored in each of the memory blocks using a map segment bitmap. The controller configures at least one memory block set by combining a set number of memory blocks, as a housekeeping event is triggered, and selects a victim block set from the at least one memory block set based on continuity of a logical address, or a number of valid map data, or both.

公开(公告)号：US11550578B2

公开(公告)日：2023-01-10

申请号：US16885011

申请日：2020-05-27

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/50 ,  G06F12/02 ,  G06F9/54

Abstract: A data storage apparatus includes a storage device; a controller to control data input and output operations of the storage device; and a swap memory provided in an outside of the controller, wherein the controller includes a thread manager to perform a preparation operation on a first thread included in a task in response to a request for processing the task, request the storage device to process the first thread on which the preparation operation has been performed, perform a preparation operation on at least one subsequent thread following the first thread while the storage device processes the first thread, and store context data of the first thread and the at least one subsequent thread in the swap memory, wherein the task includes the first thread and the at least one subsequent thread, and the preparation operation includes an address mapping operation.

公开(公告)号：US11487662B2

公开(公告)日：2022-11-01

申请号：US17375472

申请日：2021-07-14

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/08 ,  G06F12/0802

Abstract: The present technology relates to a memory controller according to an embodiment includes a map caching controller generating a slot allocation request to allocate a physical slot in which a first map segment is to be stored among a plurality of physical slots, a map buffer manager outputting the first map segment, first physical slot information, and tree slot information, in response to the slot allocation request, and a mapping manager receiving the first map segment, the first physical slot information, and the tree slot information, deleting a second map segment and second physical slot information stored in a tree slot among a plurality of tree slots of a map tree, and storing the first map segment and the first physical slot information in the tree slot. At least one of the second map segment and the second physical slot information stored in the tree slot is invalid.