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    DUTY CYCLE DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME
    11.
    发明申请
    DUTY CYCLE DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20220209751A1

    公开(公告)日：2022-06-30

    申请号：US17229348

    申请日：2021-04-13

    Applicant: SK hynix Inc.

    Inventor： Dae Ho YANG ,  Kwan Su SHON ,  Yo Han JEONG ,  Dong Shin JO

    IPC: H03K3/017

    Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210057006A1

    公开(公告)日：2021-02-25

    申请号：US16806822

    申请日：2020-03-02

    Applicant: SK hynix Inc.

    Inventor： Kwan Su SHON ,  Yo Han JEONG

    IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10

    Abstract: A semiconductor device includes a plurality of stacked dies electrically connected with each other. Each of the stacked dies includes a data path, a strobe path, a stack information generation circuit, and a delay control circuit. The data path transmits a data signal. The strobe path transmits a data strobe signal. The stack information generation circuit generates stack information representing a number of the dies. The delay control circuit controls a delay time of at least one of the data path and the strobe path to based on the stack information.

    INPUT/OUTPUT CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    13.
    发明申请
    INPUT/OUTPUT CIRCUIT AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20190287587A1

    公开(公告)日：2019-09-19

    申请号：US16194834

    申请日：2018-11-19

    Applicant: SK hynix Inc.

    Inventor： Dong Hyun KIM ,  Dae Han KWON ,  Kwan Su SHON ,  Soon Ku KANG ,  Jung Hyun SHIN ,  Doo Bock LEE ,  Yo Han JEONG ,  Eun Ji CHOI ,  Tae Jin HWANG

    IPC: G11C7/22 ,  G11C7/10

    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

    EQUALIZATION CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME
    16.
    发明申请
    EQUALIZATION CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME 有权
    平衡电路，半导体装置和使用它的半导体系统

    公开(公告)号：US20170063577A1

    公开(公告)日：2017-03-02

    申请号：US14986177

    申请日：2015-12-31

    Applicant: SK hynix Inc.

    Inventor： Kwan Su SHON ,  Yo Han JEONG

    IPC: H04L25/03

    CPC classification number: H04L25/03267 ,  H04L25/03146 ,  H04L25/063

    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

    Abstract translation: 均衡电路可以包括被配置为根据参考电压感测输入信号的缓冲器。 均衡电路可以包括被配置为产生参考电压的参考电压发生器。 参考电压可以根据输入信号的噪声而改变。

    IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    19.
    发明申请
    IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权

    公开(公告)号：US20210194485A1

    公开(公告)日：2021-06-24

    申请号：US16900537

    申请日：2020-06-12

    Applicant: SK hynix Inc.

    Inventor： Eun Ji CHOI ,  Jin Ha HWANG ,  Keun Seon AHN ,  Yo Han JEONG

    IPC: H03K19/00 ,  H03K19/0185

    Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

    DATA OUTPUT BUFFER AND MEMORY DEVICE HAVING THE SAME
    20.
    发明申请
    DATA OUTPUT BUFFER AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20190371381A1

    公开(公告)日：2019-12-05

    申请号：US16253827

    申请日：2019-01-22

    Applicant: SK hynix Inc.

    Inventor： Keun Seon AHN ,  Yo Han JEONG ,  Jin Ha HWANG

    IPC: G11C8/08 ,  G11C8/06 ,  G11C7/10 ,  G11C11/408

    Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

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