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    INPUT/OUTPUT CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    1.
    发明申请
    INPUT/OUTPUT CIRCUIT AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20190287587A1

    公开(公告)日：2019-09-19

    申请号：US16194834

    申请日：2018-11-19

    Applicant: SK hynix Inc.

    Inventor： Dong Hyun KIM ,  Dae Han KWON ,  Kwan Su SHON ,  Soon Ku KANG ,  Jung Hyun SHIN ,  Doo Bock LEE ,  Yo Han JEONG ,  Eun Ji CHOI ,  Tae Jin HWANG

    IPC: G11C7/22 ,  G11C7/10

    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

    RECEIVER CIRCUIT
    4.
    发明申请
    RECEIVER CIRCUIT 审中-公开
    接收电路

    公开(公告)号：US20150229300A1

    公开(公告)日：2015-08-13

    申请号：US14693277

    申请日：2015-04-22

    Applicant: SK hynix Inc.

    Inventor： Tae Jin HWANG

    IPC: H03K5/02 ,  H03F3/45

    CPC classification number: H03K5/02 ,  H03F3/45076 ,  H03K2005/00013 ,  H04L25/0292 ,  H04L25/03878 ,  H04L27/01

    Abstract: A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a positive intermediate output signal and a negative intermediate output signal. The second amplification unit is configured to receive the positive intermediate output signal as a positive input signal and the negative intermediate signal as a negative input signal, differentially amplify the positive and negative input signals and generate a positive output signal and a negative output signal. The first equalizing unit is configured to control the level of the negative intermediate output signal in response to the positive output signal. The second equalizing unit is configured to control the level of the positive intermediate output signal in response to the negative output signal

    Abstract translation: 接收机电路包括第一放大单元，第二放大单元，第一均衡单元和第二均衡单元。 第一放大单元被配置为差分放大输入信号和参考信号，并产生正的中间输出信号和负的中间输出信号。 第二放大单元被配置为接收正的中间输出信号作为正输入信号，负的中间信号作为负输入信号，差分地放大正输入信号和负输入信号，并产生正输出信号和负输出信号。 第一均衡单元被配置为响应于正输出信号来控制负中间输出信号的电平。 第二均衡单元被配置为响应于负输出信号来控制正中间输出信号的电平

    RECEIVER CIRCUIT
    6.
    发明申请
    RECEIVER CIRCUIT 有权
    接收电路

    公开(公告)号：US20140003482A1

    公开(公告)日：2014-01-02

    申请号：US13720424

    申请日：2012-12-19

    Applicant: SK HYNIX INC.

    Inventor： Tae Jin HWANG

    IPC: H04L27/01

    CPC classification number: H03K5/02 ,  H03F3/45076 ,  H03K2005/00013 ,  H04L25/0292 ,  H04L25/03878 ,  H04L27/01

    Abstract: A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a first intermediate output signal and a second intermediate output signal. The second amplification unit is configured to differentially amplify the first and second intermediate output signals and generate an output signal. The first equalizing unit is configured to control the level of the second intermediate output signal in response to the output signal. And the second equalizing unit is configured to control the level of the first intermediate output signal in response to the output signal.

    Abstract translation: 接收机电路包括第一放大单元，第二放大单元，第一均衡单元和第二均衡单元。 第一放大单元被配置为差分放大输入信号和参考信号，并产生第一中间输出信号和第二中间输出信号。 第二放大单元被配置为差分放大第一和第二中间输出信号并产生输出信号。 第一均衡单元被配置为响应于输出信号来控制第二中间输出信号的电平。 并且第二均衡单元被配置为响应于输出信号来控制第一中间输出信号的电平。

    BUFFER CIRCUIT AND OPERATION METHOD THEREOF
    8.
    发明申请
    BUFFER CIRCUIT AND OPERATION METHOD THEREOF 有权
    缓冲电路及其操作方法

    公开(公告)号：US20160149575A1

    公开(公告)日：2016-05-26

    申请号：US14550544

    申请日：2014-11-21

    Applicant: SK hynix Inc.

    Inventor： Tae Jin HWANG

    IPC: H03K19/003

    CPC classification number: H03K19/00384

    Abstract: A buffer circuit includes an amplification unit suitable for sensing and amplifying an input signal and a reference voltage, a buffer enable unit suitable for enabling the amplification unit based on a buffer enable signal, and a buffer enable signal generation unit suitable for generating the buffer enable signal based on a first or second operation control signal, selected according to a high voltage detection signal.

    Abstract translation: 缓冲电路包括适于感测和放大输入信号和参考电压的放大单元，适用于基于缓冲器使能信号使得放大单元能够使能的缓冲器使能单元和适于产生缓冲器使能的缓冲器使能信号生成单元 基于根据高电压检测信号选择的第一或第二操作控制信号的信号。

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