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    IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    2.
    发明申请
    IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权

    公开(公告)号：US20180019751A1

    公开(公告)日：2018-01-18

    申请号：US15377225

    申请日：2016-12-13

    Applicant: SK hynix Inc.

    Inventor： Yo Han JEONG

    IPC: H03K19/00 ,  H03K17/687

    CPC classification number: H03K19/0005 ,  H03K17/687

    Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

    SIGNAL GENERATION APPARATUS CAPABLE OF REJECTING NOISE
    5.
    发明公开
    SIGNAL GENERATION APPARATUS CAPABLE OF REJECTING NOISE 审中-公开

    公开(公告)号：US20230208410A1

    公开(公告)日：2023-06-29

    申请号：US18085333

    申请日：2022-12-20

    Applicant: SK hynix Inc.

    Inventor： Jae Hyeong HONG ,  Dae Ho YANG ,  Jun Seo JANG ,  In Seok KONG ,  Kwan Su SHON ,  Soon Sung AN ,  Yo Han JEONG

    IPC: H03K5/1252 ,  H03K19/21 ,  G06F1/06

    CPC classification number: H03K5/1252 ,  H03K19/21 ,  G06F1/06

    Abstract: A signal generation apparatus includes a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal, based on a plurality of voltage signals, to generate an output signal and adjust switching threshold voltages of the m-stage inverters, based on the plurality of voltage signals, to generate the glitch-removed output signal, when a glitch occurs in the input signal, a level detection circuit to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal, and a voltage signal generation circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch rejection circuit.

    BUFFER CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    9.
    发明申请
    BUFFER CIRCUIT AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20190296742A1

    公开(公告)日：2019-09-26

    申请号：US16164187

    申请日：2018-10-18

    Applicant: SK hynix Inc.

    Inventor： Dong Hyun KIM ,  Eun Ji CHOI ,  Yo Han JEONG ,  Jae Heung KIM

    IPC: H03K19/0185 ,  G11C7/10

    Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.

    DUTY CYCLE DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME
    10.
    发明申请
    DUTY CYCLE DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20230046522A1

    公开(公告)日：2023-02-16

    申请号：US17979583

    申请日：2022-11-02

    Applicant: SK hynix Inc.

    Inventor： Dae Ho YANG ,  Kwan Su SHON ,  Yo Han JEONG ,  Dong Shin JO

    IPC: H03K3/017 ,  G11C7/22

    Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

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